ZHCSOX6C September 2021 – December 2022 UCC14240-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| INPUT SUPPLY (Primary-side. All voltages with respect to GNDP) | ||||||
| VVIN | Input voltage range | Primary-side input voltage to GNDP | 21 | 24 | 27 | V |
| IVINQ_OFF | VIN quiescent current, disabled | VENA=0 V; VVIN = 21 V - 27 V | 700 | μA | ||
| IVIN_ON_NO_LOAD | VIN operating current, enabled, No Load | VENA = 5 V; VVIN = 21 V - 27 V; (VDD – VEE) = 25-V regulating; IVDD – VEE = 0 mA | 35 | mA | ||
| IVIN_ON_FULL_LOAD | VIN operating current, enabled, Full Load | VENA=5 V; VVIN = 21 V - 27 V; (VDD – VEE) = 25-V regulating; IVDD – VEE = 60 mA | 250 | mA | ||
| UVLOP COMPARATOR (Primary-side. All voltages with respect to GNDP) | ||||||
| VVIN_ANALOG_UVLOP_RISING | VIN analog undervoltage lockout rising threshold | 8 | 9 | 10 | V | |
| VVIN_ ANALOG_UVLOP_FALLING | VIN analog undervoltage lockout falling threshold | 7 | 8 | 9 | V | |
| VVIN_UVLOP_RISING | VIN undervoltage lockout rising threshold | 19 | 20 | 21 | V | |
| VVIN_UVLOP_FALLING | VIN undervoltage lockout falling threshold | 17.1 | 18 | 18.9 | V | |
| OVLO COMPARATOR (Primary-side. All voltages with respect to GNDP) | ||||||
| VVIN_OVLO_RISE | VIN overvoltage lockout rising threshold | 29.45 | 31 | 32.55 | V | |
| VVIN_OVLO_FALLING | VIN overvoltage lockout falling threshold | 27.55 | 29 | 30.45 | V | |
| THERMAL SHUTDOWN COMPARATOR (Primary-side) | ||||||
| TSHUTPPRIMARY_RISE | Primary-side over-temperature shutdown rising threshold (1) | First time at power-up Tj needs to be < 130 °C to turn on | 140 | 150 | 160 | °C |
| TSHUTPPRIMARY_HYST | Primary-side over-temperature shutdown hysteresis (1) | 15 | 20 | 25 | °C | |
| ENA INPUT PIN (Primary-side. All voltages with respect to GNDP) | ||||||
| VEN_IR | Input voltage rising threshold, logic HIGH | Rising edge | 2.1 | V | ||
| VEN_IF | Input voltage falling threshold, logic LOW | Falling edge | 0.8 | V | ||
| IEN | Enable Pin Input Current | VENA = 5.0 V | 5 | 10 | μA | |
| PG OPEN-DRAIN OUTPUT PIN (Primary-side. All voltages with respect to GNDP) | ||||||
| VPG_OUT_LO | PG output-low saturation voltage | Sink Current = 5 mA, power good | 0.5 | V | ||
| IPG_OUT_HI | PG Leakage current | VPG = 5.5 V, power not good | 5 | μA | ||
| FSW | Switching frequency | VVIN = 24 V; VENA = 5 V; (VDD-VEE) = 25 V | 11 | 13 | 15 | MHz |
| FSSM | Frequency of Spread Spectrum Modulation (SSM) triangle waveform | Only during primary-side startup starting after VIN > UVLOP, and ENA = HIGH; FSS_BURST_P = 1/8 μs = 125 kHz | 90 | kHz | ||
| SSM Percentage change of FCARRIER | SSM Percent change of carrier frequency during Spread Spectrum Modulation (SSM) by triangle waveform | Only during primary-side startup starting after VIN > UVLOP, and ENA = HIGH; FSS_BURST_P = 1/8 μs = 125 kHz | 5 | % | ||
| tSOFT_START_TIME_OUT | Primary-side soft-start time-out | Timer begins when VIN > UVLOP and ENA = High and reset when Powergood pin indicates Good | 16 | ms | ||
| VDD OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE) | ||||||
| VVDD_RANGE | (VDD – VEE) Output voltage range | 18 | 25 | V | ||
| VVDD_DC_ACCURACY | (VDD – VEE) Output voltage DC regulation accuracy |
Secondary-side (VDD – VEE) output voltage, over load, line and temperature range, externally adjust with external resistor divider |
-1.3 | 1.3 | % | |
| VDD REGULATION HYSTERETIC COMPARATOR (Secondary-side. All voltages with respect to VEE) | ||||||
| VFBVDD_REF | Feedback regulation reference voltage for (VDD – VEE) | (VDD – VEE) output in regulation | 2.4675 | 2.5 | 2.5325 | V |
| VFBVDD_HYST | FBVDD Hysteresis comparator hysteresis settings. Hysteresis at the FBVDD pin. [The (VDD-VEE) hysteresis would amplify this FBVDD hysteresis by the feedback resistor divider gain.] | 9 | 10 | 12.3 | mV | |
| COM OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE) | ||||||
| VVEE_RANGE | (COM – VEE) Output voltage range | 2.5 | (VDD – VEE) | V | ||
| VVEE_DC_ACCURACY | (COM – VEE) Output voltage DC regulation accuracy | Secondary-side (COM – VEE) output voltage, over load, line and temperature range, externally adjust with external resistor divider |
–1.3 | 1.3 | % | |
| COM REGULATION HYSTERETIC COMPARATOR (Secondary-side. All voltages with respect to VEE) | ||||||
| VFBVEE_REF | Feedback regulation reference voltage for (COM – VEE) | (COM – VEE) output in regulation | 2.4675 | 2.5 | 2.5325 | V |
| VRLIM_SHORT_CHRG_CMP_RISE | RLIM pin Short Charge comparator rising threshold to exit PWM | Rising threshold | 0.73 | V | ||
| tRLIM_SHORT_CHRG_ON_TIME | On-Time during RLIM pin Short Charge PWM mode | RLIM pin < 0.645 V, while FBVEE pin < 2.48 V | 1.2 | us | ||
| tRLIM_SHORT_CHRG_OFF_TIME | Off-Time during RLIM pin Short Charge PWM mode | RLIM pin < 0.645 V, while FBVEE pin < 2.48 V | 5 | us | ||
| UVLOS COMPARATOR (Secondary-side. All voltages with respect to VEE) | ||||||
| VVDD_UVLO_RISE | (VDD – VEE) undervoltage lockout rising threshold | Voltage at FBVDD | 0.9 | V | ||
| VVDD_UVLO_HYST | (VDD – VEE) undervoltage lockout hysteresis | Voltage at FBVDD | 0.2 | V | ||
| OVLOS COMPARATOR (Secondary-side. All voltages with respect to VEE) | ||||||
| VVDD_OVLOS_RISE | (VDD – VEE) overvoltage lockout rising threshold | Voltage from VDD to VEE, rising | 29.45 | 31 | 32.55 | V |
| VVDD_OVLOS_FALLING | (VDD – VEE) overvoltage lockout falling threshold | Voltage from VDD to VEE, falling | 27.55 | 29 | 30.45 | V |
| SOFT-START (Secondary-side. All voltages with respect to VEE) | ||||||
| VREF_Voltage_per_Steps | Voltage per step | 7 Steps of 200mV each, starting from 1.3V and ending at 2.5V. | 0.2 | V | ||
| VREF_Voltage_Start | VREF voltage at Start of secondary-side soft-start | 7 Steps of 200mV each, starting from 1.3V and ending at 2.5V. | 1.3 | V | ||
| VREF_Voltage_End | VREF voltage at End of secondary-side soft-start | 7 Steps of 200mV each, starting from 1.3V and ending at 2.5V. | 2.5 | V | ||
| UVP1, (VDD – VEE) UNDER -VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE) | ||||||
| VVDD_UVP_RISE | (VDD – VEE) under-voltage protection rising threshold, VUVP = VREF × 90% | 2.175 | 2.25 | 2.35 | V | |
| VVDD_UVP_HYST | (VDD – VEE) undervoltage protection hysteresis | 20 | mV | |||
| OVP1, (VDD – VEE) OVER-VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE) | ||||||
| VVDD_OVP_RISE | (VDD – VEE) over-voltage protection rising threshold, VOVP = VREF ×110% | 2.7 | 2.75 | 2.825 | V | |
| VVDD_OVP_HYST | (VDD – VEE) overvoltage protection hysteresis | 20 | mV | |||
| UVP2, (COM – VEE) UNDER -VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE) | ||||||
| VVEE_UVP_RISE | (COM – VEE) under-voltage protection rising threshold, VUVP = VREF × 90% | 2.1 | 2.25 | 2.4 | V | |
| VVEE_UVP_HYST | (COM – VEE) undervoltage protection hysteresis | 20 | mV | |||
| OVP2, (COM – VEE) OVER-VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE) | ||||||
| VVEE_OVP_RISE | (COM – VEE) over-voltage protection rising threshold, VOVP = VREF × 110% | 2.7 | 2.75 | 2.825 | V | |
| VVEE_OVP_HYST | (COM – VEE) over-voltage protection hysteresis | 20 | mV | |||
| THERMAL SHUTDOWN COMPARATOR (Secondary-side) | ||||||
| TSHUTSSECONDARY_RISE | Secondary -side over-temperature shutdown rising threshold (1) | First time at power-up Tj needs to be < 130oC to turnon. | 145 | 150 | 155 | °C |
| TSHUTSSECONDARY_HYST | Secondary-side over-temperature shutdown hysteresis (1) | 15 | 20 | 25 | °C | |
| CMTI (Common Mode Transient Immunity) | ||||||
| CMTI | Common Mode Transient Immunity | Positive VEE with respect to GNDP | 150 | V/ns | ||
| Negative VEE with respect to GNDP | –150 | V/ns | ||||
| INTEGRATED TRANSFORMER (Primary-side to Secondary-side) | ||||||
| N | Transformer effective turns ratio | Secondary side to primary side | 1.18 | - | ||