ZHCSJJ9A april 2019 – december 2020 UC1825B-SP
PRODUCTION DATA
Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correct operation of the chip. A ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents associated with the output stages. This point is the power ground to which the PGND pin is connected. Power ground can be separated from the rest of the ground plane and connected at a single point, although this is not necessary if the high di/dt paths are well understood and accounted for. VCC must be bypassed directly to power ground with a good high frequency capacitor. The sources of the power MOSFET must connect to power ground as must the return connection for input power to the system and the bulk input capacitor. The output must be clamped with a high current Schottky diode to both VCC and PGND. Nothing else should be connected to power ground.
VREF must be bypassed directly to the signal portion of the ground plane with a good high frequency capacitor. TI recommends low ESR/ESL ceramic 1-mF capacitors for both VCC and VREF. All analog circuitry must likewise be bypassed to the signal ground plane. See Figure 10-1.