ZHCSGZ9G October 2017 – November 2022 TUSB564
PRODUCTION DATA
The TUSB564 is in GPIO configuration when I2C_EN = “0”. The TUSB564 supports the following configurations: USB 3.1 only, 2 DisplayPort lanes + USB 3.1, or 4 DisplayPort lanes (no USB 3.1). The CTL1 pin controls whether DisplayPort is enabled. The combination of CTL1 and CTL0 selects between USB 3.1 only, 2 lanes of DisplayPort, or 4-lanes of DisplayPort as detailed in Table 8-2. The AUXp or AUXn to SBU1 or SBU2 mapping is controlled based on Table 8-3.
After power-up (VCC from 0 V to 3.3 V), the TUSB564 defaults to USB3.1 mode. The USB PD controller upon detecting no device attached to Type-C port or USB3.1 operation not required by attached device must take TUSB564 out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L.
| CTL1 PIN | CTL0 PIN | FLIP PIN | CONFIGURATION | VESA DisplayPort ALT MODE UFP_D CONFIGURATION |
|---|---|---|---|---|
| L | L | L | Power Down | — |
| L | L | H | Power Down | — |
| L | H | L | One Port USB 3.1 - No Flip | — |
| L | H | H | One Port USB 3.1 – With Flip | — |
| H | L | L | 4 Lane DP - No Flip | C |
| H | L | H | 4 Lane DP – With Flip | C |
| H | H | L | One Port USB 3.1 + 2 Lane DP- No Flip | D |
| H | H | H | One Port USB 3.1 + 2 Lane DP– With Flip | D |
| CTL1 PIN | FLIP PIN | MAPPING |
|---|---|---|
| H | L | SBU1 → AUXn SBU2 → AUXp |
| H | H | SBU2 → AUXn SBU1 → AUXp |
| L > 2 ms | X | Open |
Table 8-4 details the TUSB564 mux routing. This table is valid for both I2C and GPIO configuration modes.
| CTL1 PIN | CTL0 PIN | FLIP PIN | FROM | TO |
|---|---|---|---|---|
| INPUT PIN | OUTPUT PIN | |||
| L | L | L | NA | NA |
| L | L | H | NA | NA |
| L | H | L | RX1p | SSRXp |
| RX1n | SSRXn | |||
| SSTXp | TX1p | |||
| SSTXn | TX1n | |||
| L | H | H | RX2p | SSRXp |
| RX2n | SSRXn | |||
| SSTXp | TX2p | |||
| SSTXn | TX2n | |||
| H | L | L | TX2p | DP0p |
| TX2n | DP0n | |||
| RX2p | DP1p | |||
| RX2n | DP1n | |||
| RX1p | DP2p | |||
| RX1n | DP2n | |||
| TX1p | DP3p | |||
| TX1n | DP3n | |||
| H | L | H | TX1p | DP0p |
| TX1n | DP0n | |||
| RX1p | DP1p | |||
| RX1n | DP1n | |||
| RX2p | DP2p | |||
| RX2n | DP2n | |||
| TX2p | DP3p | |||
| TX2n | DP3n | |||
| H | H | L | RX1p | SSRXp |
| RX1n | SSRXn | |||
| SSTXp | TX1p | |||
| SSTXn | TX1n | |||
| TX2p | DP0p | |||
| TX2n | DP0n | |||
| RX2p | DP1p | |||
| RX2n | DP1n | |||
| H | H | H | RX2p | SSRXp |
| RX2n | SSRXn | |||
| SSTXp | TX2p | |||
| SSTXn | TX2n | |||
| TX1p | DP0p | |||
| TX1n | DP0n | |||
| RX1p | DP1p | |||
| RX1n | DP1n |