8.5 Programming
For further programmability, the TUSB546A-DCI can be controlled using I2C. The SCL and SDA pins are used for I2C clock and I2C data respectively.
Table 9. TUSB546A-DCI I2C Target Address
DPEQ0/A1
PIN LEVEL |
SSEQ0/A0
PIN LEVEL |
Bit 7 (MSB) |
Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
Bit 0 (W/R) |
| 0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0/1 |
| 0 |
R |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
0/1 |
| 0 |
F |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
0/1 |
| 0 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
0/1 |
| R |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0/1 |
| R |
R |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0/1 |
| R |
F |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0/1 |
| R |
1 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
0/1 |
| F |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0/1 |
| F |
R |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0/1 |
| F |
F |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
0/1 |
| F |
1 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
0/1 |
| 1 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0/1 |
| 1 |
R |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
0/1 |
| 1 |
F |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
0/1 |
| 1 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
0/1 |
The following procedure should be followed to write to TUSB546A-DCI I2C registers:
- The master initiates a write operation by generating a start condition (S), followed by the TUSB546A-DCI 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
- The TUSB546A-DCI acknowledges the address cycle.
- The master presents the sub-address (I2C register within TUSB546A-DCI) to be written, consisting of one byte of data, MSB-first.
- The TUSB546A-DCI acknowledges the sub-address cycle.
- The master presents the first byte of data to be written to the I2C register.
- The TUSB546A-DCI acknowledges the byte transfer.
- The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TUSB546A-DCI.
- The master terminates the write operation by generating a stop condition (P).
The following procedure should be followed to read the TUSB546A-DCI I2C registers:
- The master initiates a read operation by generating a start condition (S), followed by the TUSB546A-DCI 7-bit address and a one-value “W/R” bit to indicate a read cycle.
- The TUSB546A-DCI acknowledges the address cycle.
- The TUSB546A-DCI transmit the contents of the memory registers MSB-first starting at register 00h or last read sub-address+1. If a write to the T I2C register occurred prior to the read, then the TUSB546A-DCI shall start at the sub-address specified in the write.
- The TUSB546A-DCI shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
- If an ACK is received, the TUSB546A-DCI transmits the next byte of data.
- The master terminates the read operation by generating a stop condition (P).
The following procedure should be followed for setting a starting sub-address for I2C reads:
- The master initiates a write operation by generating a start condition (S), followed by the TUSB546A-DCI 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
- The TUSB546A-DCI acknowledges the address cycle.
- The master presents the sub-address (I2C register within TUSB546A-DCI) to be written, consisting of one byte of data, MSB-first.
- The TUSB546A-DCI acknowledges the sub-address cycle.
- The master terminates the write operation by generating a stop condition (P).
NOTE
If no sub-addressing is included for the read procedure, and reads start at register offset 00h and continue byte by byte through the registers until the I2C master terminates the read operation. If a I2C address write occurred prior to the read, then the reads start at the sub-address specified by the address write.
Table 10. Register Legend
| ACCESS TAG |
NAME |
MEANING |
| R |
Read |
The field may be read by software |
| W |
Write |
The field may be written by software |
| S |
Set |
The field may be set by a write of one. Writes of zeros to the field have no effect. |
| C |
Clear |
The field may be cleared by a write of one. Write of zero to the field have no effect. |
| U |
Update |
Hardware may autonomously update this field. |
| NA |
No Access |
Not accessible or not applicable |