ZHCSGH4B June 2017 – May 2019 TUSB546A-DCI
PRODUCTION DATA.
Figure 18. Power-Up Timing | PARAMETER | MIN | MAX | UNIT | |
|---|---|---|---|---|
| td_pg | VCC (minimum) to Internal Power Good asserted high | 500 | µs | |
| tcfg_su | CFG(1) pins setup(2) | 50 | µs | |
| tcfg_hd | CFG(1) pins hold | 10 | µs | |
| tCTL_DB | CTL[1:0] and FLIP pin debounce | 16 | ms | |
| tVCC_RAMP | VCC supply ramp requirement | 100 | ms |