ZHCSDU0F May 2015 – March 2022 TUSB320
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| tCCCB_DEFAULT | Power on default of CC1 and CC2 voltage debounce time | DEBOUCE register = 2'b00 | 133 | ms | ||
| tVBUS_DB | Debounce of VBUS_DET pin after valid VBUS_THR | 2 | ms | |||
| tDRP_DUTY_CYCLE | Power-on default of percentage of time DRP advertises DFP during a tDRP | DRP_DUTY_CYCLE register = 2'b00 | 30% | |||
| tDRP | The period during which the TUSB320 or the TUSB320I in DFP mode completes a DFP to UFP and back advertisement. | 50 | 75 | 100 | ms | |
| tI2C_EN | Time from TUSB320 EN_N low or TUSB320I EN high and VDD active to I2C access available | 100 | ms | |||
| tSOFT_RESET | Soft reset duration | 26 | 49 | 95 | ms | |
Figure 6-1 VBUS Detect and
Debounce