ZHCSKM0J November 2009 – July 2021 TUSB1210
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Analog I/O Electrical Characteristics
- 6.6 Digital I/O Electrical Characteristics
- 6.7 Digital IO Pins (Non-ULPI)
- 6.8 PHY Electrical Characteristics
- 6.9 Pullup/Pulldown Resistors
- 6.10 OTG Electrical Characteristics
- 6.11 OTG ID Electrical
- 6.12 Power Characteristics
- 6.13 Switching Characteristics
- 6.14 Timing Requirements
- 6.15 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5
Register Map
- 7.5.1 VENDOR_ID_LO
- 7.5.2 VENDOR_ID_HI
- 7.5.3 PRODUCT_ID_LO
- 7.5.4 PRODUCT_ID_HI
- 7.5.5 FUNC_CTRL
- 7.5.6 FUNC_CTRL_SET
- 7.5.7 FUNC_CTRL_CLR
- 7.5.8 IFC_CTRL
- 7.5.9 IFC_CTRL_SET
- 7.5.10 IFC_CTRL_CLR
- 7.5.11 OTG_CTRL
- 7.5.12 OTG_CTRL_SET
- 7.5.13 OTG_CTRL_CLR
- 7.5.14 USB_INT_EN_RISE
- 7.5.15 USB_INT_EN_RISE_SET
- 7.5.16 USB_INT_EN_RISE_CLR
- 7.5.17 USB_INT_EN_FALL
- 7.5.18 USB_INT_EN_FALL_SET
- 7.5.19 USB_INT_EN_FALL_CLR
- 7.5.20 USB_INT_STS
- 7.5.21 USB_INT_LATCH
- 7.5.22 DEBUG
- 7.5.23 SCRATCH_REG
- 7.5.24 SCRATCH_REG_SET
- 7.5.25 SCRATCH_REG_CLR
- 7.5.26 VENDOR_SPECIFIC1
- 7.5.27 VENDOR_SPECIFIC1_SET
- 7.5.28 VENDOR_SPECIFIC1_CLR
- 7.5.29 VENDOR_SPECIFIC2
- 7.5.30 VENDOR_SPECIFIC2_SET
- 7.5.31 VENDOR_SPECIFIC2_CLR
- 7.5.32 VENDOR_SPECIFIC1_STS
- 7.5.33 VENDOR_SPECIFIC1_LATCH
- 7.5.34 VENDOR_SPECIFIC3
- 7.5.35 VENDOR_SPECIFIC3_SET
- 7.5.36 VENDOR_SPECIFIC3_CLR
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
訂購信息
8.2.2 Device, ULPI Output Clock Mode Application
Figure 8-3 shows a suggested application diagram for TUSB1210 in the case of ULPI output clock mode (60 MHz ULPI clock is provided by TUSB1210, while link processor or another external circuit provides REFCLK), in Device mode application. Note: this is just one example, it is of course possible to operate as Device while also in ULPI input-clock mode. Refer also to Figure 8-1.
Pin 11 (CS): can be tied high to VIO
if CS_OUT pin unavailable; Pin 14 (CFG): Tied to VDDIO for 26 MHz
REFCLK mode here, tie to GND for 19.2 MHz mode.
Pin 1 (REFCLK): connect to external 3.3 V
square-wave reference clock
Ext 3 V supply supported
Pin 27 (RESETB) can be tied to VDDIO if unused.
Pins labeled N/C (no-connect) are truly no-connect, and can be tied or left floating.
Figure 8-3 Device, ULPI Output Clock Mode Application Diagram