ZHCSKM0J November 2009 – July 2021 TUSB1210
PRODUCTION DATA
| PIN | A/D | TYPE | LEVEL | DESCRIPTION | |
|---|---|---|---|---|---|
| NAME | NO. | ||||
| CFG | 14 | D | I | VDDIO | REFCLK clock frequency configuration pin. Two frequencies are supported: 19.2 MHz when 0, or 26 MHz when 1. |
| CLOCK | 26 | D | O | VDDIO | ULPI 60 MHz clock on which ULPI data is synchronized. Two modes are possible: Input Mode: CLOCK defaults as an input. Output Mode: When an input clock is detected on REFCLK pin (after 4 rising edges) then CLOCK will change to an output. |
| CPEN | 17 | D | O | VDD33 | CMOS active-high digital output control of external 5 V VBUS supply |
| CS | 11 | D | I | VDDIO | Active-high chip select pin. When low the IC is in power down and ULPI bus is tri-stated. When high normal operation. Tie to VDDIO if unused. |
| DATA0 | 3 | D | I/O | VDDIO | ULPI DATA input or output signal 0 synchronized to CLOCK |
| DATA1 | 4 | D | I/O | VDDIO | ULPI DATA input or output signal 1 synchronized to CLOCK |
| DATA2 | 5 | D | I/O | VDDIO | ULPI DATA input or output signal 2 synchronized to CLOCK |
| DATA3 | 6 | D | I/O | VDDIO | ULPI DATA input or output signal 3 synchronized to CLOCK |
| DATA4 | 7 | D | I/O | VDDIO | ULPI DATA input or output signal 4 synchronized to CLOCK |
| DATA5 | 9 | D | I/O | VDDIO | ULPI DATA input or output signal 5 synchronized to CLOCK |
| DATA6 | 10 | D | I/O | VDDIO | ULPI DATA input or output signal 6 synchronized to CLOCK |
| DATA7 | 13 | D | I/O | VDDIO | ULPI DATA input or output signal 7 synchronized to CLOCK |
| DIR | 31 | D | O | VDDIO | ULPI DIR output signal |
| DM | 19 | A | I/O | VDD33 | DM pin of the USB connector |
| DP | 18 | A | I/O | VDD33 | DP pin of the USB connector |
| ID | 23 | A | I/O | VDD33 | Identification (ID) pin of the USB connector |
| N/C | 8, 15,16, 24, 25 | — | — | — | No connection |
| NXT | 2 | D | O | VDDIO | ULPI NXT output signal |
| REFCLK | 1 | A | I | 3.3 V | VDD33 Reference clock input (square-wave only). Tie to GND when pin 26 (CLOCK) is required to be Input mode. Connect to square-wave reference clock of amplitude in the range of 3 V to 3.6 V when Pin 26 (CLOCK) is required to be Output mode. See pin 14 (CFG) description for REFCLK input frequency settings. |
| RESETB | 27 | D | I | VDDIO | When low, all digital logic (except 32 kHz logic required for power up sequencing) including registers are reset to their default values, and ULPI bus is tri-stated. When high, normal USB operation. |
| STP | 29 | D | I | VDDIO | ULPI STP input signal |
| VBAT | 21 | A | power | VBAT | Input supply voltage or battery source |
| VBUS | 22 | A | power | VBUS | VBUS pin of the USB connector |
| VDD15 | 12 | A | power | 1.5 V internal LDO output. Connect to external filtering capacitor. | |
| VDD18 | 28, 30 | A | power | VDD18 | External 1.8 V supply input. Connect to external filtering capacitor. |
| VDD33 | 20 | A | power | VDD33 | 3.3 V internal LDO output. Connect to external filtering capacitor. |
| VDDIO | 32 | A | I | VDDIO | External 1.8 V supply input for digital I/Os. Connect to external filtering capacitor. |
| GND | Thermal Pad | A | power | — | Reference Ground |