ZHCSKM0J November 2009 – July 2021 TUSB1210
PRODUCTION DATA
| PARAMETER | INPUT CLOCK | OUTPUT CLOCK | UNIT | |||
|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | |||
| ULPI Interface Timing | ||||||
| tSC, tSD | Set-up time (control in, 8-bit data in) | 3 | 6 | ns | ||
| tSC, tHD | Hold time (control in, 8-bit data in) | 1.5 | 0 | ns | ||
| tDC, tDD | Output delay (control out, 8-bit data out) | 6 | 1.2 | 5 | ns | |
| USB UART Interface Timing | ||||||
| tPH_DP_CON | Phone D+ connect time | 100 | ms | |||
| tPH_DISC_DET | Phone D+ disconnect time | 150 | ms | |||
| fUART_DFLT | Default UART signaling rate (typical rate) | 9600 | bps | |||
Figure 6-1 TUSB1210 Power-Up Timing (ULPI Clock Input Mode)| PARAMETER | COMMENTS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| tDEL_CS_SUPPLYOK | Chip-select-to-supplies OK delay | 2.84 | 4.10 | ms | ||
| tDEL_RST_DIR | RESETB to PHY PLL locked and DIR falling-edge delay | 0.54 | 0.647 | ms | ||
| tVBBDET | VBAT detection delay | 10 | μs | |||
| tBGAP | Bandgap power-on delay | 2 | ms | |||
| tPWONVDD15 | VDD15 power-on delay | 100 | μs | |||
| tPWONCK32K | 32-KHz RC-OSC power-on delay | 125 | μs | |||
| tDELRSTPWR | Power control reset delay | 61 | μs | |||
| tDELMNTRVIOEN | Monitor enable delay | 91.5 | μs | |||
| tMNTR | Supply monitoring debounce | 183.1 | μs | |||
| tDELVDD33EN | VDD33 LDO enable delay | 93.75 | μs | |||
| tDELRESETB | RESETB internal delay | 244.1 | μs | |||
| tPLL | PLL lock time | 300 | μs | |||