SLLSFB2 April 2020 TUSB1146
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 TUSB1146 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Supply Characteristics
- 6.6 Control I/O DC Electrical Characteristics
- 6.7 USB and DP Electrical Characteristics
- 6.8 DCI Electrical Characteristics
- 6.9 Timing Requirements
- 6.10 Switching Characteristics
- 6.11 Typical Characteristics
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1
TUSB1146 Registers
- 8.6.1.1 General_1 Register (Offset = 0xA) [reset = 0x1]
- 8.6.1.2 DCI_TXEQ_CTRL Register (Offset = 0xB) [reset = 0x6C]
- 8.6.1.3 DP01EQ_SEL Register (Offset = 0x10) [reset = 0x0]
- 8.6.1.4 DP23EQ_SEL Register (Offset = 0x11) [reset = 0x0]
- 8.6.1.5 DisplayPort_1 Register (Offset = 0x12) [reset = 0x0]
- 8.6.1.6 DisplayPort_2 Register (Offset = 0x13) [reset = 0x0]
- 8.6.1.7 AEQ_CONTROL1 Register (Offset = 0x1C) [reset = 0xF0]
- 8.6.1.8 AEQ_CONTROL2 Register (Offset = 0x1D) [reset = 0x20]
- 8.6.1.9 AEQ_LONG Register (Offset = 0x1E) [reset = 0x77]
- 8.6.1.10 USBC_EQ Register (Offset = 0x20) [reset = 0x0]
- 8.6.1.11 SS_EQ Register (Offset = 0x21) [reset = 0x0]
- 8.6.1.12 USB3_MISC Register (Offset = 0x22) [reset = 0x44]
- 8.6.1.13 USB_STATUS Register (Offset = 0x24) [reset = 0x41]
- 8.6.1.14 VOD_CTRL Register (Offset = 0x32) [reset = 0x40]
- 8.6.1.15 AEQ_STATUS Register (Offset = 0x3B) [reset = 0x0]
- 8.6.1
TUSB1146 Registers
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
5 TUSB1146 Pin Configuration and Functions
RNQ Package
40-Pin (WQFN)
Top View
TUSB1146 Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| DP0p | 9 | Diff I | DP Differential positive input for DisplayPort Lane 0. |
| DP0n | 10 | Diff I | DP Differential negative input for DisplayPort Lane 0. |
| DP1p | 12 | Diff I | DP Differential positive input for DisplayPort Lane 1. |
| DP1n | 13 | Diff I | DP Differential negative input for DisplayPort Lane 1. |
| DP2p | 15 | Diff I | DP Differential positive input for DisplayPort Lane 2. |
| DP2n | 16 | Diff I | DP Differential negative input for DisplayPort Lane 2. |
| DP3p | 18 | Diff I | DP Differential positive input for DisplayPort Lane 3. |
| DP3n | 19 | Diff I | DP Differential negative input for DisplayPort Lane 3. |
| RX1n | 31 | Diff I/O | Differential negative output for DisplayPort or differential negative input for USB3.1 Downstream Facing port. |
| RX1p | 30 | Diff I/O | Differential positive output for DisplayPort or differential positive input for USB3.1 Downstream Facing port. |
| TX1n | 34 | Diff O | Differential negative output for DisplayPort or USB3.1 downstream facing port. |
| TX1p | 33 | Diff O | Differential positive output for DisplayPort or USB 3.1 downstream facing port. |
| TX2p | 37 | Diff O | Differential positive output for DisplayPort or USB 3.1 downstream facing port. |
| TX2n | 36 | Diff O | Differential negative output for DisplayPort or USB 3.1 downstream facing port. |
| RX2p | 40 | Diff I/O | Differential positive output for DisplayPort or differential positive input for USB3.1 Downstream Facing port. |
| RX2n | 39 | Diff I/O | Differential negative output for DisplayPort or differential negative input for USB3.1 Downstream Facing port. |
| SSTXp | 8 | Diff I | Differential positive input for USB3.1 upstream facing port. |
| SSTXn | 7 | Diff I | Differential negative input for USB3.1 upstream facing port. |
| SSRXp | 5 | Diff O | Differential positive output for USB3.1 upstream facing port. |
| SSRXn | 4 | Diff O | Differential negative output for USB3.1 upstream facing port. |
| EQ1 | 35 | 4 Level I | This pin along with EQ0 sets the USB receiver equalizer gain for downstream facing RX1 and RX2 when USB used. Refer to Table 7 for details on the equalization setting. |
| EQ0 | 38 | 4 Level I | This pin along with EQ1 sets the USB receiver equalizer gain for downstream facing RX1 and RX2 when USB used. Refer to Table 7 for details on the equalization setting. |
| CAD_SNK/DCI_DAT(1) | 29 | I/O
(PD) |
When I2C_EN ! = 0, this pin functions as DCI data output Leave open if not used. When I2C_EN = 0 , this pin is CAD_SNK (L = AUX snoop enabled and H = AUX snoop disabled with all lanes active). |
| HPDIN/DCI_CLK(1) | 32 | I/O
(PD) |
When I2C_EN ! = 0, this pin functions as DCI clock output Leave open if not used. When I2C_EN = 0, this pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is Low for greater than 2ms, all DisplayPort lanes are disabled while the AUX to SBU switch will remain closed. |
| I2C_EN | 17 | 4 Level I | I2C Programming Mode or GPIO Programming Select.
0 = GPIO mode (I2C disabled) with adaptive EQ disabled. R = TI Test Mode (I2C enabled at 3.3 V) F = I2C enabled at 1.8 V when EQ0 = "0" and EQ1 = "0". All other combinations of EQ0 and EQ1 are reserved. 1 = I2C enabled at 3.3 V. |
| SBU1 | 27 | I/O, CMOS | SBU1. This pin should be DC coupled to the SBU1 pin on the Type-C receptacle. A 2-M ohm resistor to GND is also recommended. |
| SBU2 | 26 | I/O, CMOS | SBU2. This pin should be DC coupled to the SBU2 pin on the Type-C receptacle. A 2-M ohm resistor to GND is also recommended. |
| AUXp | 24 | I/O, CMOS | AUXp. DisplayPort AUX positive I/O connected to the DisplayPort source through a AC coupling capacitor. In addition to AC coupling capacitor, this pin also requires a 100K resistor to GND. This pin along with AUXN is used by the TUSB1146 for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C. |
| AUXn | 25 | I/O, CMOS | AUXn. DisplayPort AUX negative I/O connected to the DisplayPort source through a AC coupling capacitor. In addition to AC coupling capacitor, this pin also requires a 100K resistor to VCC (3.3V). This pin along with AUXP is used by the TUSB1146 for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C. |
| DPEQ1 | 2 | 4 Level I | DisplayPort Receiver EQ. Along with DPEQ0, this pin selects the DisplayPort receiver equalization gain. Refer to Table 9 for details on the equalization settings. |
| DPEQ0/A1 | 14 | 4 Level I | DisplayPort Receiver EQ. Along with DPEQ1, this pin selects the DisplayPort receiver equalization gain. When I2C_EN is not ‘0’, this pin will also set the TUSB1146 I2C address. Refer to Table 9 for details on the equalization settings. |
| SSEQ1 | 3 | 4 Level I | Along with SSEQ0, sets the USB receiver equalizer gain for upstream facing SSTXP/N. Refer to Table 8 for details on the equalization settings. |
| SSEQ0/A0 | 11 | 4 Level I | Along with SSEQ1, sets the USB receiver equalizer gain for upstream facing SSTXP/N. When I2C_EN is not ‘0’, this pin will also set the TUSB1146 I2C address. Refer to Table 8 for details on the equalization settings. |
| FLIP/SCL | 21 | 2 Level I | When I2C_EN=’0’ this is Flip control pin, otherwise this pin is I2C clock. . When used for I2C clock pull-up to I2C master's VCC I2C supply. |
| CTL0/SDA | 22 | 2 Level I | When I2C_EN=’0’ this is a USB3.1 Switch control pin, otherwise this pin is I2C data. When used for I2C data pullup to I2C master's VCC I2C supply. |
| CTL1/HPDIN | 23 | 2 Level I
(Failsafe) (PD) |
DP Alt mode Switch Control Pin. When I2C_EN = ‘0’, this pin will enable or disable DisplayPort functionality. Otherwise, when I2C_EN is not "0", DisplayPort functionality is enabled and disabled through I2C registers.
L = DisplayPort Disabled. H = DisplayPort Enabled. When I2C_EN is not "0" this pin is an input for Hot Plug Detect received from DisplayPort sink. When this HPDIN is Low for greater than 2 ms, all DisplayPort lanes are disabled and AUX to SBU switch will remain closed. |
| VCC | 1, 6, 20, 28 | P | 3.3-V Power Supply |
| Thermal Pad | G | Ground | |
(1) Not a fail-safe I/O. Actively driving pin high while VCC is removed results in leakage voltage on VCC pins.