SLLSFB2 April 2020 TUSB1146
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 TUSB1146 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Supply Characteristics
- 6.6 Control I/O DC Electrical Characteristics
- 6.7 USB and DP Electrical Characteristics
- 6.8 DCI Electrical Characteristics
- 6.9 Timing Requirements
- 6.10 Switching Characteristics
- 6.11 Typical Characteristics
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1
TUSB1146 Registers
- 8.6.1.1 General_1 Register (Offset = 0xA) [reset = 0x1]
- 8.6.1.2 DCI_TXEQ_CTRL Register (Offset = 0xB) [reset = 0x6C]
- 8.6.1.3 DP01EQ_SEL Register (Offset = 0x10) [reset = 0x0]
- 8.6.1.4 DP23EQ_SEL Register (Offset = 0x11) [reset = 0x0]
- 8.6.1.5 DisplayPort_1 Register (Offset = 0x12) [reset = 0x0]
- 8.6.1.6 DisplayPort_2 Register (Offset = 0x13) [reset = 0x0]
- 8.6.1.7 AEQ_CONTROL1 Register (Offset = 0x1C) [reset = 0xF0]
- 8.6.1.8 AEQ_CONTROL2 Register (Offset = 0x1D) [reset = 0x20]
- 8.6.1.9 AEQ_LONG Register (Offset = 0x1E) [reset = 0x77]
- 8.6.1.10 USBC_EQ Register (Offset = 0x20) [reset = 0x0]
- 8.6.1.11 SS_EQ Register (Offset = 0x21) [reset = 0x0]
- 8.6.1.12 USB3_MISC Register (Offset = 0x22) [reset = 0x44]
- 8.6.1.13 USB_STATUS Register (Offset = 0x24) [reset = 0x41]
- 8.6.1.14 VOD_CTRL Register (Offset = 0x32) [reset = 0x40]
- 8.6.1.15 AEQ_STATUS Register (Offset = 0x3B) [reset = 0x0]
- 8.6.1
TUSB1146 Registers
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
7 Parameter Measurement Information
Figure 17. I2C Timing Diagram Definitions 
Figure 18. USB3.1 to 4-Lane DisplayPort in GPIO Mode 
Figure 19. Propagation Delay 
Figure 20. Electrical Idle Mode Exit and Entry Delay 
Figure 21. Output Rise and Fall Times 
Figure 22. AUX to SBU Switch ON Timing Diagram 
Figure 23. AUX to SBU Switch OFF Timing Diagram 
Figure 24. DCI Clock Propagation Delay 
Figure 25. SSRX Limited De-emphasis Only 
Figure 26. SSRX Limited Pre-Shoot Only 
Figure 27. Power-On Timing