SLLSFB2 April 2020 TUSB1146
PRODUCTION DATA.
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| USB3.1 | ||||||
| tIDLEEntry | Delay from U0 to electrical idle | Refer to Figure 20. | 10 | ns | ||
| tIDELExit_U1 | U1 exist time: break in electrical idle to the transmission of LFPS | Refer to Figure 20. | 6 | ns | ||
| tIDLEExit_U2U3 | U2/U3 exit time: break in electrical idle to transmission of LFPS | Refer to Figure 20. | 10 | µs | ||
| tRXDET_INTVL | RX detect interval while in Disconnect | 12 | ms | |||
| tIDLEExit_DISC | Disconnect Exit Time | 10 | µs | |||
| tExit_SHTDN | Shutdown Exit Time | 1 | ms | |||
| tAEQ_FULL_DONE | Maximum time to obtain optimum EQ setting when operating in Full AEQ mode. | 300 | µs | |||
| tAEQ_FAST_DONE | Maximum time to determine appropriate EQ setting when operating in Fast AEQ mode. | 60 | µs | |||
| tDIFF_DLY | Differential Propagation Delay | Refer to Figure 19. | 300 | ps | ||
| tR, tF | Output Rise/Fall time | 20%-80% of differential voltage measured 1.7 inch from the output pin; Refer to Figure 21. | 40 | ps | ||
| tRF_MM | Output Rise/Fall time mismatch | 20%-80% of differential voltage measured 1.7 inch from the output pin | 2.6 | ps | ||
| Power-up | ||||||
| tD_PG | VCC(min) to internal Power Good asserted high | Refer to Figure 27 | 25 | ms | ||
| tCFG_SU | CFG(1) pins setup(2) | Refer to Figure 27 | 250 | µs | ||
| tCFG_HD | CFG(1) pins hold | Refer to Figure 27 | 10 | µs | ||
| tCTL_DB | CTL[1:0] and FLIP pin debounce | Refer to Figure 27 | 16 | ms | ||