ZHCSNL3A December 2021 – November 2023 TPSM8D6C24
PRODUCTION DATA
| CMD Address | 64h |
| Write Transaction: | Write Word |
| Read Transaction: | Read Word |
| Format: | SLINEAR11 per CAPABILITY |
| Phased: | No |
| NVM Backup: | EEPROM |
| Updates: | On-the-fly |
The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received (as programmed by the ON_OFF_CONFIG command) until the unit stops transferring energy to the output.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RW | RW | RW | RW | RW | RW | RW | RW |
| TOFFDLY_EXP | TOFFDLY_MAN | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RW | RW | RW | RW | RW | RW | RW | RW |
| TOFFDLY_MAN | |||||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 15:11 | TOFFDLY_ EXP | RW | 11111b | Linear format two’s complement exponent |
| 10:0 | TOFFDLY_ MAN | RW | NVM | Linear format two’s complement mantissa |
Attempts to write (64h) TOFF_DELAY beyond the supported range are considered invalid or unsupported data and cause the TPSM8D6C24 to respond by flagging the appropriate status bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3. TOFF_DELAY supports values from 0 ms to 127.5 ms in 0.5-ms steps. An internal delay of up to 50 μs is added to TOFF_DELAY, even if TOFF_DELAY is equal to 0 ms.