ZHCSNL3A December 2021 – November 2023 TPSM8D6C24
PRODUCTION DATA
Using Equation 20, the maximum input RMS current is 12.8 A and the input capacitors must be rated to handle this. When calculating this, the maximum output current should be divided by the number of phases. The output current is divided by the number of phases because the switching nodes are interleaved. Interleaving the switching node effectively divides the amplitude of the current pulses the input capacitor by the number of phases. With the 16-V maximum input in this example, a ceramic capacitor with at least a 25-V voltage rating is required to support the maximum input voltage.
For this design, allow 0.1-V input ripple for VRIPPLE(cap) and 0.2-V input ripple for VRIPPLE(esr). Using Equation 21 and Equation 22, the minimum input capacitance for this design is 31.8 μF and the maximum ESR is 5.02 mΩ, respectively. Again, the maximum output current should be divided by the number of phases and the calculated capacitance must be placed near the loop controller converter and all of the loop follower converters. Eight 22-μF, 25-V ceramic capacitors and six 6800-pF, 25-V ceramic capacitors in parallel were selected to bypass the power stage with sufficient margin. Additionally, four 100-μF, 25-V low-ESR electrolytic capacitors were placed on the input to minimize deviations on the input during transients. These capacitors are distributed equally between the phases. To minimize the high frequency ringing, the high frequency 6800-pF PVIN bypass capacitors must be placed close to power stage.
When stacking converters the amount of input RMS current and the amount if input capacitance required can be further reduced. The amount of ripple cancellation depends on the number of phases and the duty cycle. PCB inductance between the phases can also reduce the effects of ripple cancellation. The calculations given in this example ignore the effects of ripple cancellation.