ZHCSNL3A December 2021 – November 2023 TPSM8D6C24
PRODUCTION DATA
The TPSM8D6C24 supports the 100-kHz, 400-kHz, and 1-MHz bus speeds. Connection for the PMBus interface must follow the high power DC specifications given in section 3.1.3 in the SMBus specification V2.0 for the 400-kHz bus speed or the low power DC specifications in section 3.1.2. The complete SMBus specification is available from the SMBus web site, smiforum.org
The PMBus interface pins PMB_CLK, PMB_DATA, and SMB_ALRT require external pullup resistors to a 1.8-V to 5.5-V termination. Size the pullup resistors to meet the minimize rise-time required for the desired PMBus clock speed but should not source more current than the lowest-rated CLK, DATA, or SMB_ALRT pin on the bus when the bus voltage is forced to 0.4 V. The TPSM8D6C24 supports a minimum of 20 mA of sink current on PMB_CLK, PMB_DATA, and SMB_ALRT.