ZHCSG68F MARCH 2017 – JANUARY 2019 TPSM846C23
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 PMBus
- 7.3.2 Minimum Capacitance Requirements
- 7.3.3 Setting the Compensation Network
- 7.3.4 Transient Response
- 7.3.5 Setting the Output Voltage via PMBus
- 7.3.6 Setting the Output Voltage Without PMBus
- 7.3.7 Differential Remote Sense
- 7.3.8 Voltage Reference
- 7.3.9 Switching Frequency and Synchronization
- 7.3.10 Input Undervoltage Lockout (UVLO)
- 7.3.11 Turnon and Turnoff Delay and Sequencing
- 7.3.12 Soft-Start Time and TON_RISE Command
- 7.3.13 Soft-Stop Time and TOFF_FALL Command
- 7.3.14 Prebiased Output Start-Up
- 7.3.15 Power Good (PGOOD) Indicator
- 7.3.16 Linear Regulators BP3 and BP6
- 7.3.17 VREF_TRIM
- 7.3.18 MARGIN
- 7.3.19 Parallel Application
- 7.3.20 Parallel Operation
- 7.3.21 Telemetry
- 7.3.22 Overtemperature Protection
- 7.3.23 Overcurrent Protection
- 7.3.24 Output Overvoltage and Undervoltage Protection
- 7.3.25 Fault Protection Responses
- 7.4 Device Functional Modes
- 7.5
Register Maps
- 7.5.1 OPERATION (01h)
- 7.5.2 ON_OFF_CONFIG (02h)
- 7.5.3 CLEAR_FAULTS (03h)
- 7.5.4 WRITE_PROTECT (10h)
- 7.5.5 STORE_DEFAULT_ALL (11h)
- 7.5.6 RESTORE_DEFAULT_ALL (12h)
- 7.5.7 STORE_USER_ALL (15h)
- 7.5.8 RESTORE_USER_ALL (16h)
- 7.5.9 CAPABILITY (19h)
- 7.5.10 SMBALERT_MASK (1Bh)
- 7.5.11 VOUT_MODE (20h)
- 7.5.12 VOUT_COMMAND (21h)
- 7.5.13 VOUT_MAX (24h)
- 7.5.14 VOUT_TRANSITION_RATE (27h)
- 7.5.15 VOUT_SCALE_LOOP (29h)
- 7.5.16 VOUT_MIN (2Bh)
- 7.5.17 VIN_ON (35h)
- 7.5.18 VIN_OFF (36h)
- 7.5.19 IOUT_CAL_OFFSET (39h)
- 7.5.20 VOUT_OV_FAULT_RESPONSE (41h)
- 7.5.21 VOUT_UV_FAULT_RESPONSE (45h)
- 7.5.22 IOUT_OC_FAULT_LIMIT (46h)
- 7.5.23 IOUT_OC_FAULT_RESPONSE (47h)
- 7.5.24 IOUT_OC_WARN_LIMIT (4Ah)
- 7.5.25 OT_FAULT_LIMIT (4Fh)
- 7.5.26 OT_FAULT_RESPONSE (50h)
- 7.5.27 OT_WARN_LIMIT (51h)
- 7.5.28 TON_DELAY (60h)
- 7.5.29 TON_RISE (61h)
- 7.5.30 TON_MAX_FAULT_LIMIT (62h)
- 7.5.31 TON_MAX_FAULT_RESPONSE (63h)
- 7.5.32 TOFF_DELAY (64h)
- 7.5.33 TOFF_FALL (65h)
- 7.5.34 STATUS_BYTE (78h)
- 7.5.35 STATUS_WORD (79h)
- 7.5.36 STATUS_VOUT (7Ah)
- 7.5.37 STATUS_IOUT (7Bh)
- 7.5.38 STATUS_INPUT (7Ch)
- 7.5.39 STATUS_TEMPERATURE (7Dh)
- 7.5.40 STATUS_CML (7Eh)
- 7.5.41 STATUS_MFR_SPECIFIC (80h)
- 7.5.42 READ_VOUT (8Bh)
- 7.5.43 READ_IOUT (8Ch)
- 7.5.44 READ_TEMPERATURE_1 (8Dh)
- 7.5.45 PMBUS_REVISION (98h)
- 7.5.46 IC_DEVICE_ID (ADh)
- 7.5.47 IC_DEVICE_REV (AEh)
- 7.5.48 MFR_SPECIFIC_00 (D0h)
- 7.5.49 VREF_TRIM (MFR_SPECIFIC_04) (D4h)
- 7.5.50 STEP_VREF_MARGIN_HIGH (MFR_SPECIFIC_05) (D5h)
- 7.5.51 STEP_VREF_MARGIN_LOW (MFR_SPECIFIC_06) (D6h)
- 7.5.52 PCT_OV_UV_WRN_FLT_LIMITS (MFR_SPECIFIC_07) (D7h)
- 7.5.53 OPTIONS (MFR_SPECIFIC_21) (E5h)
- 7.5.54 MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h)
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.3.11 Turnon and Turnoff Delay and Sequencing
The TPSM846C23 device provides many sequencing options. Using the ON_OFF_CONFIG command, the device can be configured to start up whenever the input voltage is above the UVLO threshold, to require an additional signal on the CNTL pin, to receive an update to the OPERATION command through the PMBus interface, or a combination of these configurations. When the gating signal as specified by the ON_OFF_CONFIG command is asserted, a programmable turnon delay can be set with the TON_DELAY command to delay the start of power conversion. Similarly, a programmable turnoff delay can be set with the TOFF_DELAY command to delay the stop of power delivery once the gating signal is deasserted. Delay times are specified in milliseconds (ms), from 0 to 100 ms.
The TPSM846C23, as supplied by the factory, is programmed for zero TOFF_DELAY and 3-ms TOFF_FALL parameters. The power stage discharges the output capacitors when CNTL is de-asserted or under a fault condition. Note that the power stage sinks current as it ramps the output voltage to zero. Once the output voltage is ramped to approximately 200 mV, the power stage will tri-state. This default behavior is set by the ON_OFF_CONFIG command register. The user can set the cpa bit if a controlled soft-stop discharge of the output capacitors is not desired. If this bit is set, the power stage is immediately tri-stated when CNTL is de-asserted or when a fault occurs. The load on the regulator output provides the only means of discharging the output capacitors.
Figure 16 shows control of the start-up and shutdown operations of the device when the device is configured to respond to both the CNTL signal and the OPERATION command. The device can also be configured to independently use either the CNTL signal or the OPERATION command or to convert power when a sufficient input voltage is available.
