The TPSI2240-Q1 is specifically designed to support dielectric withstand testing. In a high voltage system, a dielectric withstand test (HiPot) may be administered during the characterization, production or maintenance of the system to validate the reliability of the insulation barriers and galvanically isolated domains it contains. These withstand voltage tests intentionally stress the components spanning these domains and put them in an overvoltage condition. MOSFETs that are placed under these overvoltage conditions will enter avalanche mode and begin conducting current at a high voltage, dissipating high power and heating up. TPSI2240T-Q1 integrates Thermal Avalanche Protection (TAP). When the internal temperature of the IC increases beyond T_TAP this mode will enable. In this mode, the device will enable and disable the main power FET to regulate its internal temperature and be able to sustain higher avalance currents. The design and qualification of the TPSI2240T-Q1 was completed with this state in mind and supports up to 3mA I_AVA for 60 second intervals, while the TPSI2240-Q1 supports up to 1mA I_AVA for 60 second intervals.

The dielectric withstand test voltage (V_HiPot), the TPSI2240-Q1's avalanche voltage (V_AVA), and the resistance (R) in series with the TPSI2240-Q1 should be chosen to limit the avalanche current (I_AVA) to the corresponding current limit depending on the test duration. In addition, the PCB design should follow the recommendations in the Layout Guidelines section to ensure adequate thermal performance to keep the junction temperature (T_J) below the absolute maximum rating of the TPSI2240-Q1.

Figure 9-10 Dielectric Withstand Test (HiPot) - Simplified Schematic