ZHCSL08C October 2019 – August 2021 TPS8804
PRODUCTION DATA
Table 7-3 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 7-3 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0h | REVID | Device Information | Go |
| 1h | STATUS1 | Status 1 | Go |
| 2h | STATUS2 | Status 2 | Go |
| 3h | MASK | Interrupt Mask | Go |
| 4h | CONFIG1 | Config 1 | Go |
| 5h | CONFIG2 | Config 2 | Go |
| 6h | ENABLE1 | Enable 1 | Go |
| 7h | ENABLE2 | Enable 2 | Go |
| 8h | CONTROL | Control | Go |
| Bh | GPIO_AMUX | GPIO and AMUX | Go |
| Ch | COSW | CO Switch | Go |
| Dh | CO | CO Amplifier | Go |
| Fh | LEDLDO | LED LDO | Go |
| 10h | PH_CTRL | Photo Amplifier | Go |
| 11h | LED_DAC_A | LED DAC A | Go |
| 12h | LED_DAC_B | LED DAC B | Go |
Complex bit access types are encoded to fit into small table cells. Table 7-4 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| RC | R C | Read to Clear |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |