ZHCSMK8A December 2020 – April 2021 TPS7B87-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
訂購信息
8.1.4.2 Power Dissipation Versus Ambient Temperature
Figure 8-6 is based off of a JESD51-7 4-layer, high-K board. The allowable power dissipation was estimated using the following equation. As discussed in the An empirical analysis of the impact of board layout on LDO thermal performance application report, thermal dissipation can be improved in the JEDEC high-K layout by adding top layer copper and increasing the number of thermal vias. If a good thermal layout is used, the allowable thermal dissipation can be improved by up to 50%.
Equation 4. 
Figure 8-6 TPS7B87-Q1 Allowable Power
Dissipation