ZHCSMK8A December 2020 – April 2021 TPS7B87-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
訂購信息
7.3.2 Adjustable Power-Good Delay Timer (DELAY)
The power-good delay period is a function of the external capacitor on the DELAY pin. The adjustable delay configures the amount of time required before the PG pin becomes high. This delay is configured by connecting an external capacitor from this pin to GND. Figure 7-2 shows the typical timing diagram for the power-good delay pin. If the DELAY pin is left floating, the power-good delay is t(DLY_FIX). For more information on how to program the PG delay, see the Section 8.1.7.1 section.
V(PG_TH) falling = V(PG_TH) rising – V(PG_HYST)..
Figure 7-2 Typical Power-Good Timing Diagram