ZHCSLG3C June 2020 – August 2022 TPS7B86-Q1
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
-
8 Application and Implementation
- 8.1 Application Information
- 8.2 Typical Application
- 8.3 Power Supply Recommendations
- 8.4 Layout
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
8.1.6.2 Power Dissipation Versus Ambient Temperature
Figure 8-6 is based off of a JESD51-7 4-layer, high-K board. The allowable power dissipation was estimated using the following equation. As discussed in the An empirical analysis of the impact of board layout on LDO thermal performance application note, thermal dissipation can be improved in the JEDEC high-K layout by adding top layer copper and increasing the number of thermal vias. If a good thermal layout is used, the allowable thermal dissipation can be improved by up to 50%.
Equation 8. 
Figure 8-6 TPS7B86-Q1 Allowable Power
Dissipation