ZHCSLG3C June 2020 – August 2022 TPS7B86-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
-
8 Application and Implementation
- 8.1 Application Information
- 8.2 Typical Application
- 8.3 Power Supply Recommendations
- 8.4 Layout
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
訂購信息
8.1.6.1 Thermal Performance Versus Copper Area
The most used thermal resistance parameter RθJA is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in the Section 6.4 table is determined by the JEDEC standard (see Figure 8-1), PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper.
Figure 8-1 JEDEC Standard 2s2p PCBFigure 8-2 through Figure 8-5 illustrate the functions of RθJA and ψJB versus copper area and thickness. These plots are generated with a 101.6-mm × 101.6-mm × 1.6-mm PCB of two and four layers. For the 4-layer board, inner planes use 1-oz copper thickness. Outer layers are simulated with both 1-oz and 2-oz copper thickness. A 2x3 (DDA package) or a 3×4 (KVU package) array of thermal vias with a 300-μm drill diameter and 25-μm copper plating is located beneath the thermal pad of the device. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first inner GND plane. Each of the layers has a copper plane of equal area.
Figure 8-2 RθJA vs Copper
Area (DDA Package)
Figure 8-4 RθJA vs Copper
Area (KVU Package)
Figure 8-3 ψJB vs Copper
Area (DDA Package)
Figure 8-5 ψJB vs Copper
Area (KVU Package)