ZHCSI96J March 2010 – March 2020 TPS7A60-Q1 , TPS7A61-Q1
PRODUCTION DATA.
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| ENABLE | 4 | I | Enable pin (for TPS7A61-Q1 only): This is a high-voltage-tolerant input pin with an internal pulldown. A high input to this pin activates the device and turns the regulator ON. This input can be connected to the VIN pin for self-bias applications. If this pin is not connected, the device stays disabled. |
| GND | 3 | I/O | Ground pin: This is the signal-ground pin of the IC. |
| nRST | 2 | O | Reset pin: This is an output pin with an external pullup resistor connected to the VOUT pin. |
| RDELAY | 4 | O | Reset delay timer pin (for TPS7A60-Q1 only): This pin is used to program the reset delay timer using an external capacitor (CDLY) to ground. |
| VIN | 1 | I | Input voltage pin: The unregulated input voltage is supplied to this pin. A bypass capacitor is connected between the VIN pin and the GND pin to dampen input line transients. |
| VOUT | 5 | O | Regulated output-voltage pin: This is a regulated voltage output (VOUT = 3.3 V or 5 V, as applicable) pin with a limitation on maximum output current. In order to achieve stable operation and prevent oscillation, an external output capacitor (COUT) with low ESR is connected between this pin and the GND pin. |