ZHCSPG4D december 2021 – august 2023 TPS7A14
PRODUCTION DATA
- 1
- 1特性
- 2應用
- 3說明
- 4Revision History
- 5Pin Configuration and Functions
- 6Specifications
- 7Detailed Description
-
8Application and Implementation
- 8.1
Application Information
- 8.1.1 Recommended Capacitor Types
- 8.1.2 Input, Output, and Bias Capacitor Requirements
- 8.1.3 Dropout Voltage
- 8.1.4 Behavior During Transition From Dropout Into Regulation
- 8.1.5 Device Enable Sequencing Requirement
- 8.1.6 Load Transient Response
- 8.1.7 Undervoltage Lockout Circuit Operation
- 8.1.8 Power Dissipation (PD)
- 8.1.9 Estimating Junction Temperature
- 8.1.10 Recommended Area for Continuous Operation
- 8.2 Typical Application
- 8.3 Power Supply Recommendations
- 8.4 Layout
- 8.1
Application Information
- 9Device and Documentation Support
- Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數據表獲取器件具體的封裝圖。
機械數據 (封裝 | 引腳)
- DRV|6
- YBK|6
散熱焊盤機械數據 (封裝 | 引腳)
訂購信息
5 Pin Configuration and Functions
Figure 5-1 YBK Package,6-Pin WCSP(Top View)Table 5-1 Pin Functions: YBK Package
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| A1 | OUT | Output | Regulated output pin. A 2.2-μF or greater capacitance is required from OUT to ground for stability. For best transient response, use an 8-μF (nominal) or larger ceramic capacitor from OUT to ground. Place the output capacitor as close to OUT as possible. |
| A2 | IN | Input | Input pin. A 0.75-μF or greater capacitance is required from IN to ground for stability. Place the input capacitor as close to IN as possible. |
| B1 | SENSE | Input | SENSE input. This pin is a feedback input to the regulator for SENSE connections. Connecting SENSE to the load helps eliminate voltage errors resulting from trace resistance between OUT and the load. |
| B2 | EN | Input | Enable pin. Driving this pin to logic high enables the LDO. Driving this pin to logic low disables the LDO. If enable functionality is not required, EN must be connected to IN or BIAS. |
| C1 | GND | — | Ground pin. This pin must be connected to ground. |
| C2 | BIAS | Input | BIAS pin. This pin enables operation in low-input voltage, low-output voltage (LILO) conditions. For best performance, use 0.47-μF or larger ceramic capacitor from BIAS to ground. Place the bias capacitor as close to BIAS as possible. |
Figure 5-2 DRV Package,6-Pin WSON With Exposed Thermal Pad(Top View)Table 5-2 Pin Functions: DRV Package
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | OUT | Output | Regulated output pin. A 2.2-μF or greater capacitance is required from OUT to ground for stability. For best transient response, use an 8-μF (nominal) or larger ceramic capacitor from OUT to ground. Place the output capacitor as close to OUT as possible. |
| 2 | SENSE | Input | SENSE input. This pin is a feedback input to the regulator for SENSE connections. Connecting SENSE to the load helps eliminate voltage errors resulting from trace resistance between OUT and the load. |
| 3 | EN | Input | Enable pin. Driving this pin to logic high enables the LDO. Driving this pin to logic low disables the LDO. If enable functionality is not required, EN must be connected to IN or BIAS. |
| 4 | BIAS | Input | BIAS pin. This pin enables operation in LILO conditions. For best performance, use 0.47-μF or larger ceramic capacitor from BIAS to ground. Place the bias capacitor as close to BIAS as possible. |
| 5 | GND | — | Ground pin. This pin must be connected to ground. |
| 6 | IN | Input | Input pin. A 0.75-μF or greater capacitance is required from IN to ground for stability. Place the input capacitor as close to IN as possible. |
| Thermal Pad | — | The thermal pad is electrically connected to the GND node. Connect to the GND plane for improved thermal performance. | |