ZHCSI93D May 2018 – October 2022 TPS65987D
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
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6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Supply Requirements and Characteristics
- 6.6 Power Consumption Characteristics
- 6.7 Power Switch Characteristics
- 6.8 Cable Detection Characteristics
- 6.9 USB-PD Baseband Signal Requirements and Characteristics
- 6.10 BC1.2 Characteristics
- 6.11 Thermal Shutdown Characteristics
- 6.12 Oscillator Characteristics
- 6.13 I/O Characteristics
- 6.14 PWM Driver Characteristics
- 6.15 I2C Requirements and Characteristics
- 6.16 SPI Controller Timing Requirements
- 6.17 HPD Timing Requirements
- 6.18 Typical Characteristics
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 USB-PD Physical Layer
- 8.3.2 Power Management
- 8.3.3 Port Power Switches
- 8.3.4 Cable Plug and Orientation Detection
- 8.3.5 Dead Battery Operation
- 8.3.6 Battery Charger Detection and Advertisement
- 8.3.7 ADC
- 8.3.8 DisplayPort HPD
- 8.3.9 Digital Interfaces
- 8.3.10 PWM Driver
- 8.3.11 Digital Core
- 8.3.12 I2C Interfaces
- 8.3.13 SPI Controller Interface
- 8.3.14 Thermal Shutdown
- 8.3.15 Oscillators
- 8.4 Device Functional Modes
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9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Type-C VBUS Design Considerations
- 9.2.2 Notebook Design Supporting PD Charging
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
9.2.2.2.2.4 RESETN
Figure 9-8 RESETN CircuitThe TPS65987D and the Thunderbolt controller share the same flash and they must be able to access it at different times. The TPS65987D will access the flash first to load its configuration and then the Thunderbolt controller will read the flash for its firmware. The TPS65987D will hold the Thunderbolt controller in reset until it has read its configuration from the flash. GPIO_0 is reserved to act as the reset signal for the Thunderbolt controller. The RESET_N (Thunderbolt Controller Master Reset) signal must also be gated by the 3.3-V supply to the Thunderbolt controller (VCC3P3_SX). When the RESET_N signal is de-asserted before the supply has come up it may put the Thunderbolt controller in a latched state. The RESET_N signal must be de-asserted at least 100 μs after the Thunderbolt Controller supply has come up. For dead battery operation the GPIO_0 signal should be “ANDed” with the 3.3-V supply to avoid de-asserting the RESETN when the Thunderbolt controller is not powered. The figure below shows the RESET_N control with GPIO_0 and the 3.3-V supply. Alternatively, the EC could configure GPIO_0 to de-assert RESETN when the system has successfully booted.