ZHCSD04E November 2014 – March 2022 TPS65400
PRODUCTION DATA
OVP, OCP, and undervoltage protection (UVP) are handled for each switcher independently. OVP or OCP faults that occur on one switcher do not affect the other outputs. There are two exceptions:
During the soft-start time for a switcher, all fault signals (OVP, OCP, and UVP) are disabled and reset to the unfaulted condition. The first moment when faults can be triggered is after the end of the soft-start sequence.
OVP thresholds are set as a percentage of VREF. A deglitching time of 50 μs is used for the overvoltage. When an overvoltage occurs at the OVP upper threshold limit, the high-side FET and the low-side FET are disabled for that switcher until the OVP falling threshold is reached. When the OVP falling threshold is reached, the low-side FET turns on for 200 ns to ensure that the bootstrap capacitor is recharged before resuming normal operation of the converter.
Output voltage falling below the UVP thresholds causes the corresponding PGOOD output to fall, but the switcher continues to operate as it tries to increase the output voltage. However, if the PGOOD terminal is tied to the enable ENSWx signal of another switcher on the PCB (for external sequencing), the output for that ENSWx-PGOOD-tied switcher is disabled until output voltage is nominal and PGOOD is good.
OTP shuts down all switchers. When the temperature drops below the hysteresis level, a soft reset is triggered and the chip restarts from the startup sequence.
Section 8.5.2.4 describes fault reporting and clearing of fault status registers.
The OVP and UVP sensing is deglitched to prevent unwanted tripping. The faults need to be sustained for more than 55 μs typically (60 μs max) to be registered and trigger protection circuits and PGOOD output to fall. Fault detection is disabled on a given switcher when its VREF is being ramped (as result of an I2C command to change VREF). An additional 100-μs fault blanking time results after VREF has been adjusted to its target level.