ZHCSD04E November 2014 – March 2022 TPS65400
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VLINEREG | Line regulation | 0.1 | %/V | |||
| VLOADREG | Load regulation | 0.1 | %/A | |||
| tr | VOUT step duration (tr) | For 50-mV step | 30 | μs | ||
| ts | VOUT step settling time (ts) | For 50-mV step | 30 | μs | ||
| VOVUV | VOUT step overshoot/undershoot | For 50-mV step | 6 | mV | ||
| Efficiency (SW1 and SW2) | VIN = 5 V, VO = 1.2 V, IOUT = 4 A, ?sw = 500 kHz | 77% | ||||
| VIN = 12 V, VO = 1.2 V, IOUT = 4
A, ?sw = 500 kHz | 76% | |||||
| Efficiency (SW3 and SW4) | VIN = 5 V, VO = 1.2 V, IOUT = 2 A, ?sw= 500 kHz | 77% | ||||
| VIN = 12 V, VO = 1.2 V, IOUT = 2
A, ?sw= 500 kHz | 74% | |||||
| IOUTmatch | Average ((1)) current sharing accuracy (SW1 and SW2, SW3 and SW4) | Iload = IOUTmax | 20% | |||
| IPKmatch | Peak current ((2)) sharing accuracy (SW1 and SW2, SW3 and SW4) | Iload = IOUTmax | 20% | |||
| tacc | Timing accuracy for delays and restarts | –10% | 10% | |||
| treset_delay | Time after RSTn or CE is released for power sequence to begin | Default value | 1 | ms | ||
| treset_delay_max0 | Minimum delay after reset is released for power sequence to begin | treset_delay set to 0 ms | 1.1 | ms | ||