6 Pin Configuration and Functions

A. Thermal pad must be soldered to PCB as SW3 and SW4 power ground.

Figure 6-1 48-Pin VQFNRGZ Package(Top View)

Table 6-1 Pin Functions

PIN		DESCRIPTION
NAME	NO.	DESCRIPTION
CB1	1	Bootstrap pin for the high-side MOSFET gate drive for SW1
SW1	2	Switch pin for SW1
	3
	4
PVIN1	5	Power input for the buck switching regulator SW1
PVIN2	6	Power input for SW2
PGND1	7	Power ground for buck converters
PGND2	8	Power ground for buck converters
SW2	9	Switch pin for SW2
	10
	11
CB2	12	Bootstrap pin for the SW2 high-side MOSFET gate drive
ENSW2	13	Enable input pin for SW2. Active high. A 2-μA internal pullup current is inside.
VFB2	14	Feedback input pin for SW2
COMP2	15	Compensation pin for external compensation network for SW2. Pulling this line high to VDDA configures the SW1 controller to control both SW1 and SW2.
SS2/PG2	16	Soft start for SW2 (default). A capacitor is used to set the start-up time. This pin can also be reconfigured through I²C to display the PGOOD2 signal instead.
PGOOD	17	Default PGOOD signal is for all switchers. It can be changed according to (D2h) PIN_CONFIG_00. If all switchers are disabled, PGOOD is low.
VDDG	18	Supply for gate drives. Bypass locally to PGND.
VDDA	19	Output of internal regulator for analog controls
VDDD	20	3.3-V output of internal regulator digital controls
AGND	21	Ground connection for analog controls
VIN	22	Analog V_IN. Power input pin for the VDDD, VDDA, and VGATE subregulator power
CE	23	Chip enables. Internal pullup current will default to high if the pin is left floating. Connect to an open-drain output to pull low to disable. Driving with a push-pull output is not recommended. When low, internal regulators are shutdown to minimize power, and functions are disabled. Configuration is reloaded from EEPROM as part of the power-up sequence when CE goes high.
SS3/PG3	24	Soft-start for SW3 (default). A capacitor is used to set the startup time. This pin can also be reconfigured through I²C to display the PGOOD3 signal instead.
COMP3	25	Compensation pin for external compensation network for SW3
VFB3	26	Feedback input pin for SW3
ENSW3	27	Enable input pin for SW3. Active high. A 2-μA internal pullup current is inside.
CB3	28	Bootstrap pin for SW3 high-side MOSFET gate drive
SW3	29	Switch pin for SW3. The maximum rated output current is 2 A.
PVIN3	30	Power input for buck switching regulator SW3
PVIN4	31	Power input for SW4
SW4	32	Switch pin for SW4. The maximum rated output current is 2 A.
CB4	33	Bootstrap pin for SW4 high-side MOSFET gate drive
ENSW4	34	Enable input pin for SW4. Active high. A 2-μA internal pullup current is inside.
VFB4	35	Feedback input pin for SW4
COMP4	36	Compensation pin for external compensation network for SW4. Pulling this line high to VDDA configures the SW3 controller to control both SW3 and SW4.
SS4/PG4	37	Soft start for SW4 (default). A capacitor is used to set the start-up time. This pin can also be reconfigured through I²C to display the PGOOD4 signal instead.
I2CADDR	38	Select I²C address with a resistor to AGND.
RST_N	39	Reset of digital logic. When low, all switchers are disabled. Configuration is reloaded from EEPROM when RESET_N is deasserted.
RCLOCK_SYNC	40	Resistor for setting primary clock frequency from 275 kHz to 2.2 MHz or for clock sync
I2CALERT	41	Open-drain output that is pulled low for 200 μs when a timeout condition is detected by the I²C watchdog on either SDA or SCL.
SDA	42	Data input/output pin for I²C bus
SCL	43	Clock input pin for I²C bus
CLK_OUT	44	Clock output signal. Open-collector output, requires pull up
SS1/PG1	45	Soft start for SW1 (default). A capacitor is used to set the start-up time. This pin can also be reconfigured through I²C to display the PGOOD1 signal instead.
COMP1	46	Compensation pin for external compensation network for SW1
VFB1	47	Feedback input pin for SW1
ENSW1/ENSEQ	48	Enable input pin for SW1. Active high. A 2-μA internal pullup current is inside.