ZHCSNM6A May 2021 – August 2021 TPS6521855
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1
Wake-Up and Power-Up and Power-Down Sequencing
- 7.3.1.1 Power-Up Sequencing
- 7.3.1.2 Power-Down Sequencing
- 7.3.1.3 Strobe 1 and Strobe 2
- 7.3.1.4 Supply Voltage Supervisor and Power-Good (PGOOD)
- 7.3.1.5 Internal LDO (INT_LDO)
- 7.3.1.6 Current Limited Load Switches
- 7.3.1.7 LDO1
- 7.3.1.8 UVLO
- 7.3.1.9 Power-Fail Comparator
- 7.3.1.10 DCDC3 and DCDC4 Power-Up Default Selection
- 7.3.1.11 I/O Configuration
- 7.3.1.12 Push Button Input (PB)
- 7.3.1.13 AC_DET Input (AC_DET)
- 7.3.1.14 Interrupt Pin (INT)
- 7.3.1.15 I2C Bus Operation
- 7.3.1
Wake-Up and Power-Up and Power-Down Sequencing
- 7.4 Device Functional Modes
- 7.5 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.3.1.12 Push Button Input (PB)
The PB pin is a CMOS-type input used to power-up the PMIC. Typically, the PB pin is connected to a momentary switch to ground and an external pullup resistor. The power-up sequence is triggered if the PB input is held low for 600 ms.
Figure 7-18 Left: Typical PB Input Circuit Right: Push-Button
Input (PB) Deglitch and Power-Up TimingIn ACTIVE mode, the TPS6521855 monitors the PB input and issues an interrupt when the pin status changes, such as when it drops below or rises above the PB input-low or input-high thresholds. The interrupt is masked by the PBM bit in the INT_MASK1 register.
Figure 7-19 PB
Input-Low or Input-High ThresholdsInterrupts are issued whenever the PB pin status changes. The PB_STATE bit reflects the current status of the PB input. nWAKEUP is pulled low for 150 μs on every falling edge of PB.