ZHCSNM6A May 2021 – August 2021 TPS6521855
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1
Wake-Up and Power-Up and Power-Down Sequencing
- 7.3.1.1 Power-Up Sequencing
- 7.3.1.2 Power-Down Sequencing
- 7.3.1.3 Strobe 1 and Strobe 2
- 7.3.1.4 Supply Voltage Supervisor and Power-Good (PGOOD)
- 7.3.1.5 Internal LDO (INT_LDO)
- 7.3.1.6 Current Limited Load Switches
- 7.3.1.7 LDO1
- 7.3.1.8 UVLO
- 7.3.1.9 Power-Fail Comparator
- 7.3.1.10 DCDC3 and DCDC4 Power-Up Default Selection
- 7.3.1.11 I/O Configuration
- 7.3.1.12 Push Button Input (PB)
- 7.3.1.13 AC_DET Input (AC_DET)
- 7.3.1.14 Interrupt Pin (INT)
- 7.3.1.15 I2C Bus Operation
- 7.3.1
Wake-Up and Power-Up and Power-Down Sequencing
- 7.4 Device Functional Modes
- 7.5 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.3.1.4 Supply Voltage Supervisor and Power-Good (PGOOD)
Power-good (PGOOD) is an open-drain output of the built-in voltage supervisor that monitors DCDC1, DCDC2, DCDC3, DCDC4, and LDO1. The output is Hi-Z when all enabled rails are in regulation and driven low when one or more rails encounter a fault which brings the output voltage outside the specified tolerance range. In a typical application PGOOD drives the reset signal of the SOC.
The supervisor has two modes of operation, controlled by the STRICT bit. With the STRICT bit set to 0, all enabled rails of the five regulators are monitored for undervoltage only with relaxed thresholds and deglitch times. With the STRCT bit set to 1, all enabled rails of the five regulators are monitored for undervoltage and overvoltage with tight limits and short deglitch times. Table 7-1 summarizes these details.
| PARAMETER | STRICT = 0b (TYP) | STRICT =1b (TYP) | |
|---|---|---|---|
| Undervoltage monitoring | Threshold (output falling) | 90% | 96.5% (DCDC1 and DCDC2) 95.5% (DCDC3, DCDC4, and LDO1) |
| Deglitch (output falling) | 1 ms | 50 μs | |
| Deglitch (output rising) | 10 μs | 10 μs | |
| Overvoltage monitoring | Threshold (output falling) | N/A | 103.5% (DCDC1 and DCDC2) 104.5% (DCDC3, DCDC4, and LDO1) |
| Deglitch (output falling) | N/A | 1 ms | |
| Deglitch (output rising) | N/A | 50 μs | |
Figure 7-7 Definition of Undervoltage, Overvoltage Thresholds, Hysteresis, and Deglitch
TimesThe following rules apply to the PGOOD output:
- The power-up default state for THE PGOOD is low. When all rails are disabled, the PGOOD output is driven low.
- Only enabled rails are monitored. Disabled rails are ignored.
- Power-good monitoring of a particular rail starts 5 ms after the rail is enabled and is continuously monitored thereafter. This allows the rail to power-up.
- The PGOOD is delayed by PGDLY time after the sequencer is finished and the last rail is enabled.
- If an enabled rail is continuously outside the monitoring threshold for longer than the deglitch time, then the PGOOD is pulled low, and all rails are shut-down following the power-down sequence. PGDLY does not apply.
- Disabling a rail manually by resetting the DCx_EN or LDO1_EN bit has no effect on the PGOOD pin. If all rails are disabled, the PGOOD is driven low as the last rail is disabled.
- If the power-down sequencer is triggered, PGOOD is driven low.
- The PGOOD is driven low in the SUSPEND state, regardless of the number of rails that are enabled.
#SLDS2067476 shows a typical power-up sequence and PGOOD timing.
