ZHCSI15L June 2006 – May 2018 TPS65023 , TPS65023B
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3
- 6.7 Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
- 6.8 Electrical Characteristics: VDCDC1 Step-Down Converter
- 6.9 Electrical Characteristics: VDCDC2 Step-Down Converter
- 6.10 Electrical Characteristics: VDCDC3 Step-Down Converter
- 6.11 I2C Timing Requirements for TPS65023B
- 6.12 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 VRTC Output and Operation With or Without Backup Battery
- 7.3.2 Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
- 7.3.3 Power Save Mode Operation
- 7.3.4 Low Ripple Mode
- 7.3.5 Soft-Start
- 7.3.6 100% Duty Cycle Low Dropout Operation
- 7.3.7 Active Discharge When Disabled
- 7.3.8 Power-Good Monitoring
- 7.3.9 Low-Dropout Voltage Regulators
- 7.3.10 Undervoltage Lockout
- 7.3.11 Power-Up Sequencing
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1 VERSION Register Address: 00h (Read Only)
- 7.6.2 PGOODZ Register Address: 01h (Read Only)
- 7.6.3 MASK Register Address: 02h (Read and Write), Default Value: C0h
- 7.6.4 REG_CTRL Register Address: 03h (Read and Write), Default Value: FFh
- 7.6.5 CON_CTRL Register Address: 04h (Read and Write), Default Value: B1h
- 7.6.6 CON_CTRL2 Register Address: 05h (Read and Write), Default Value: 40h
- 7.6.7 DEFCORE Register Address: 06h (Read and Write), Default Value: 14h/1Eh
- 7.6.8 DEFSLEW Register Address: 07h (Read and Write), Default Value: 06h
- 7.6.9 LDO_CTRL Register Address: 08h (Read and Write), Default Value: Set with DEFLDO1 and DEFLDO2
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSB|40
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSB|40
訂購信息
7.5.2 Serial Interface
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to 400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as VCC remains above 2 V. The TPS65023x has a 7-bit address: 1001000, other addresses are available upon contact with the factory. Attempting to read data from the register addresses not listed in this section results in FFh being read out.
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS65023x device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS65023x device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS65023x device must leave the data line high to enable the master to generate the stop condition. See I2C Timing Requirements for TPS65023B for more information.
Figure 31. Bit Transfer on the Serial Interface 
Figure 32. START and STOP Conditions 
Figure 33. Serial I/F WRITE to TPS65023x Device 
Figure 34. Serial I/F READ from TPS65023x: Protocol A 
Figure 35. Serial I/F READ from TPS65023x: Protocol B