ZHCSI15L June 2006 – May 2018 TPS65023 , TPS65023B
PRODUCTION DATA.
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The TPS65023x power-up sequencing is designed to be entirely flexible and customer driven. This is achieved by providing separate enable pins for each switch-mode converter, and a common enable signal for the LDOs. The relevant control pins are described in Table 2.
| PIN NAME | I/O | FUNCTION |
|---|---|---|
| DEFDCDC3 | I | Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to 1.8 V, DEFDCDC3 = VCC defaults VDCDC3 to 3.3 V. |
| DEFDCDC2 | I | Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to 1.8 V, DEFDCDC2 = VCC defaults VDCDC2 to 3.3 V. |
| DEFDCDC1 | I | Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 1.2 V, DEFDCDC1 = VCC defaults VDCDC1 to 1.6 V. |
| DCDC3_EN | I | Set DCDC3_EN = 0 to disable and DCDC3_EN = 1 to enable the VDCDC3 converter |
| DCDC2_EN | I | Set DCDC2_EN = 0 to disable and DCDC2_EN = 1 to enable the VDCDC2 converter |
| DCDC1_EN | I | Set DCDC1_EN = 0 to disable and DCDC1_EN = 1 to enable the VDCDC1 converter |
| HOT_RESET | I | The HOT_RESET pin generates a reset (RESPWRON) for the processor.HOT_RESET does not alter any TPS65023x settings except the output voltage of VDCDC1. Activating HOT_RESET sets the voltage of VDCDC1 to its default value defined with the DEFDCDC1 pin. HOT_RESET is internally de-bounced by the TPS65023x. |
| RESPWRON | O | RESPWRON is held low when power is initially applied to the TPS65023x. The VRTC voltage is monitored: RESWPRON is low when VRTC < 2.4 V and remains low for a time defined by the external capacitor at the TRESPWRON pin. RESPWRON can also be forced low by activation of the HOT_RESET pin. |
| TRESPWRON | I | Connect a capacitor here to define the RESET time at the RESPWRON pin (1 nF typically gives 100 ms). |