| SWITCHING REGULATOR |
| AGND1 |
40 |
— |
Analog ground. All analog ground pins are connected internally on the chip |
| AGND2 |
17 |
— |
Analog ground. All analog ground pins are connected internally on the chip |
| DCDC1_EN |
25 |
I |
VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator |
| DCDC2_EN |
24 |
I |
VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator |
| DCDC3_EN |
23 |
I |
VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator |
| DEFDCDC1 |
10 |
I |
Input for signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V. DEFDCDC1 can also be connected to a resistor divider between VDCDC1 and GND, if the output voltage of the DCDC1 converter is set in a range from 0.6 V to VINDCDC1 V. |
| DEFDCDC2 |
32 |
I |
Input for signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 3.3 V. DEFDCDC2 can also be connected to a resistor divider between VDCDC2 and GND, if the output voltage of the DCDC2 converter is set in a range from 0.6 V to VINDCDC2 V. |
| DEFDCDC3 |
1 |
I |
Input for signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V. DEFDCDC3 can also be connected to a resistor divider between VDCDC3 and GND, if the output voltage of the DCDC3 converter is set in a range from 0.6 V to VINDCDC3 V. |
| L1 |
7 |
— |
Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here. |
| L2 |
35 |
— |
Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here |
| L3 |
4 |
— |
Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here |
| PGND1 |
8 |
— |
Power ground for VDCDC1 converter |
| PGND2 |
34 |
— |
Power ground for VDCDC2 converter |
| PGND3 |
3 |
— |
Power ground for VDCDC3 converter |
| VCC |
37 |
I |
Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 DC-DC converters. VCC must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2. VCC also supplies serial interface block. |
| VDCDC1 |
9 |
I |
VDCDC1 feedback voltage sense input. Connect directly to VDCDC1 |
| VDCDC2 |
33 |
I |
VDCDC2 feedback voltage sense input. Connect directly to VDCDC2 |
| VDCDC3 |
2 |
I |
VDCDC3 feedback voltage sense input. Connect directly to VDCDC3 |
| VINDCDC1 |
6 |
I |
Input for VDCDC1 step-down converter. VINDCDC1 must be connected to the same voltage supply as VINDCDC2, VINDCDC3, and VCC |
| VINDCDC2 |
36 |
I |
Input for VDCDC2 step-down converter. VINDCDC2 must be connected to the same voltage supply as VINDCDC1, VINDCDC3, and VCC |
| VINDCDC3 |
5 |
I |
Input for VDCDC3 step-down converter. VINDCDC3 must be connected to the same voltage supply as VINDCDC1, VINDCDC2, and VCC |
| Thermal pad |
— |
— |
Connect the thermal pad to analog ground |
| LDO REGULATOR |
| DEFLD01 |
12 |
I |
Digital input. DEFLD01 sets the default output voltage of LDO1 and LDO2 |
| DEFLD02 |
13 |
I |
Digital input. DEFLD02 sets the default output voltage of LDO1 and LDO2 |
| LDO_EN |
22 |
I |
Enable input for LDO1 and LDO2. A logic high enables the LDOs, a logic low disables the LDOs |
| VBACKUP |
15 |
I |
Connect the backup battery to this input pin |
| VINLDO |
19 |
I |
Input for LDO1 and LDO2 |
| VLDO1 |
20 |
O |
Output of LDO1 |
| VLDO2 |
18 |
O |
Output of LDO2 |
| VRTC |
16 |
O |
Output of the LDO/switch for the real time clock |
| VSYSIN |
14 |
I |
Input of system voltage for VRTC switch |
| CONTROL AND I2C |
| HOT_RESET |
11 |
I |
Push-button input that reboots or wakes up the processor through RESPWRON output pin |
| INT |
28 |
O |
Open drain output |
| LOW_BAT |
21 |
O |
Open-drain output of LOW_BAT comparator |
| LOWBAT_SNS |
39 |
I |
Input for the comparator driving the LOW_BAT output |
| PWRFAIL |
31 |
O |
Open-drain output. Active low when PWRFAIL comparator indicates low VBAT condition |
| PWRFAIL_SNS |
38 |
I |
Input for the comparator driving the PWRFAIL output |
| RESPWRON |
27 |
O |
Open-drain system reset output |
| SCLK |
30 |
I |
Serial interface clock line |
| SDAT |
29 |
I/O |
Serial interface data/address |
| TRESPWRON |
26 |
I |
Connect the timing capacitor to TRESPWRON to set the reset delay time: 1 nF → 100 ms. |