ZHCSIH9F March 2009 – July 2018 TPS65023-Q1
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| CONTROL SIGNALS: SCLK, SDAT (INPUT), DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2 | ||||||||
| VIH | High-level input voltage | Resistor pullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC | 1.3 | VCC | V | |||
| VIH | High-level input voltage, SDAT | Resistor pullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC | 1.45 | VCC | V | |||
| VIL | Low-level input voltage | Resistor pullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC | 0 | 0.4 | V | |||
| IH | Input bias current | 0.01 | 0.1 | μA | ||||
| CONTROL SIGNALS: HOT_RESET | ||||||||
| VIH | High-level input voltage | 1.3 | VCC | V | ||||
| VIL | Low-level input voltage | 0 | 0.4 | V | ||||
| IIB | Input bias current | 0.01 | 0.1 | μA | ||||
| tglitch | Deglitch time at HOT_RESET | 25 | 30 | 35 | ms | |||
| CONTROL SIGNALS: LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (OUTPUT) | ||||||||
| VOH | High-level output voltage | 6 | V | |||||
| VOL | Low-level output voltage | IIL = 5 mA | 0 | 0.3 | V | |||
| Duration of low pulse at RESPWRON | External capacitor 1 nF | 100 | ms | |||||
| Reset power-on threshold | VRTC falling | –3% | 2.4 | 3% | V | |||
| VRTC rising | –3% | 2.52 | 3% | |||||
| SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3 | ||||||||
| I(q) | Operating quiescent current, PFM | All three DC-DC converters enabled, zero load, no switching, and LDOs enabled | VCC = 3.6 V,
VBACKUP = 3 V, VSYSIN = 0 V |
85 | 100 | μA | ||
| All three DC-DC converters enabled, zero load, no switching, and LDOs off | VCC = 3.6 V,
VBACKUP = 3 V, VSYSIN = 0 V |
78 | 90 | |||||
| DCDC1 and DCDC2 converters enabled, zero load, no switching, and LDOs off | VCC = 3.6 V,
VBACKUP = 3 V, VSYSIN = 0 V |
57 | 70 | |||||
| DCDC1 converter enabled, zero load, no switching, and LDOs off | VCC = 3.6 V,
VBACKUP = 3 V, VSYSIN = 0 V |
43 | 55 | |||||
| II | Current into VCC, PWM | All three DC-DC converters enabled and running in PWM, LDOs off | VCC = 3.6 V,
VBACKUP = 3 V, VSYSIN = 0 V |
2 | 3 | mA | ||
| DCDC1 and DCDC2 converters enabled and running in PWM, LDOs off | VCC = 3.6 V,
VBACKUP = 3 V, VSYSIN = 0 V |
1.5 | 2.5 | |||||
| DCDC1 converter enabled and running in PWM, LDOs off | VCC = 3.6 V,
VBACKUP = 3 V, VSYSIN = 0 V |
0.85 | 2 | |||||
| I(q) | Quiescent current | All converters disabled, LDOs off | VCC = 3.6 V,
VBACKUP = 3 V, VSYSIN = 0 V |
23 | 33 | μA | ||
| VCC = 2.6 V,
VBACKUP = 3 V, VSYSIN = 0 V |
3.5 | 5 | ||||||
| VCC = 3.6 V,
VBACKUP = 0 V, VSYSIN = 0 V |
43 | |||||||
| SUPPLY PINS: VBACKUP, VSYSIN, VRTC | ||||||||
| I(q) | Operating quiescent current | VBACKUP = 3 V, VSYSIN = 0 V, VCC = 2.6 V,
current into VBACKUP |
20 | 33 | μA | |||
| I(SD) | Operating quiescent current | VBACKUP < V_VBACKUP, current into VBACKUP | 2 | 3 | μA | |||
| VRTC LDO output voltage | VSYSIN = VBACKUP = 0 V, IO = 0 mA | 3 | V | |||||
| IO | Output current for VRTC | VSYSIN < 2.57 V and VBACKUP < 2.57 V | 30 | mA | ||||
| VRTC short-circuit current limit | VRTC = GND, VSYSIN = VBACKUP = 0 V | 100 | mA | |||||
| Maximum output current at VRTC for
RESPWRON = 1 |
VRTC > 2.6 V, VCC = 3 V, VSYSIN = VBACKUP = 0 V | 30 | mA | |||||
| VO | Output voltage accuracy for VRTC | VSYSIN = VBACKUP = 0 V, IO = 0 mA | –1% | 1% | ||||
| Line regulation for VRTC | VCC = VRTC + 0.5 V to 6.5 V, IO = 5 mA | –1% | 1% | |||||
| Load regulation VRTC | IO = 1 mA to 30 mA, VSYSIN = VBACKUP = 0 V | –3% | 1% | |||||
| Regulation time for VRTC | Load change from 10% to 90% | 10 | μs | |||||
| Ilkg | Input leakage current at VSYSIN | VSYSIN < V_VSYSIN | 2 | μA | ||||
| rDS(on) of VSYSIN switch | 12.5 | Ω | ||||||
| rDS(on) of VBACKUP switch | 12.5 | Ω | ||||||
| Input voltage range at VBACKUP(1) | 2.73 | 3.75 | V | |||||
| Input voltage range at VSYSIN(1) | 2.73 | 3.75 | V | |||||
| VSYSIN threshold | VSYSIN falling | –3% | 2.55 | 3% | V | |||
| VSYSIN threshold | VSYSIN rising | –3% | 2.65 | 3% | V | |||
| VBACKUP threshold | VBACKUP falling | –3% | 2.55 | 3% | V | |||
| VBACKUP threshold | VBACKUP falling | –3% | 2.65 | 3% | V | |||
| SUPPLY PIN: VINLDO | ||||||||
| I(q) | Operating quiescent current | Current per LDO into VINLDO | 16 | 30 | μA | |||
| I(SD) | Shutdown current | Total current for both LDOs into VINLDO, VINLDO = 0 V | 0.1 | 1 | μA | |||
| VDCDC1 STEP-DOWN CONVERTER | ||||||||
| IO | Maximum output current | 1500 | mA | |||||
| I(SD) | Shutdown supply current in VINDCDC1 | DCDC1_EN = GND | 0.1 | 1 | μA | |||
| rDS(on) | P-channel MOSFET on-resistance | VCC = V(GS) = 3.6 V | 125 | 261 | mΩ | |||
| Ilkg | P-channel leakage current | VCC = 6 V | 2 | μA | ||||
| rDS(on) | N-channel MOSFET on-resistance | VCC = V(GS) = 3.6 V | 130 | 260 | mΩ | |||
| Ilkg | N-channel leakage current | V(DS) = 6 V | 7 | 10 | μA | |||
| Forward current limit (P-channel and N-channel) | 2.5 V < VI(MAIN) < 6 V | 1.9 | 2.19 | 2.6 | A | |||
| fS | Oscillator frequency | 1.95 | 2.25 | 2.55 | MHz | |||
| Fixed output voltage FPWMDCDC1 = 0 | All VDCDC1 | VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1.5 A | –2% | 2% | ||||
| Fixed output voltage FPWMDCDC1 = 1 | VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1.5 A | –1% | 1% | |||||
| Adjustable output voltage with resistor divider at DEFDCDC1, FPWMDCDC1 = 0 | VCC = VDCDC1 + 0.3 V (minimum 2.5 V) to 6 V,
0 mA ≤ IO ≤ 1.2 A |
–2% | 2% | |||||
| Adjustable output voltage with resistor divider at DEFDCDC1, FPWMDCDC1 = 1 | VCC = VDCDC1 + 0.3 V (minimum 2.5 V) to 6 V,
0 mA ≤ IO ≤ 1.2 A |
–1% | 1% | |||||
| Line regulation | VCC = VDCDC1 + 0.3 V (minimum. 2.5 V) to 6 V, IO = 10 mA | 0 | %/V | |||||
| Load regulation | IO = 10 mA to 1200 mA | 0.25 | %/A | |||||
| Soft-start ramp time | VDCDC1 ramping from 5% to 95% of target value | 750 | μs | |||||
| Internal resistance from L1 to GND | 1 | MΩ | ||||||
| VDCDC1 discharge resistance | DCDC1 discharge = 1 | 300 | Ω | |||||
| VDCDC2 STEP-DOWN CONVERTER | ||||||||
| IO | Maximum output current | DEFDCDC2 = GND | 1200 | mA | ||||
| VCC = 3.6 V, 3.3 V – 1% ≤ VDCDC2 ≤ 3.3 V + 1% | 1000 | |||||||
| I(SD) | Shutdown supply current in VINDCDC2 | DCDC2_EN = GND | 0.1 | 1 | μA | |||
| rDS(on) | P-channel MOSFET on-resistance | VCC = V(GS) = 3.6 V | 140 | 300 | mΩ | |||
| Ilkg | P-channel leakage current | VCC = 6 V | 2 | μA | ||||
| rDS(on) | N-channel MOSFET on-resistance | VCC = V(GS) = 3.6 V | 150 | 297 | mΩ | |||
| Ilkg | N-channel leakage current | V(DS) = 6 V | 7 | 10 | μA | |||
| ILIMF | Forward current limit (P-channel and N-channel) | 2.5 V < VCC < 6 V | 1.7 | 1.94 | 2.2 | A | ||
| fS | Oscillator frequency | 1.95 | 2.25 | 2.55 | MHz | |||
| Fixed output voltage FPWMDCDC2=0 | VDCDC2 = 1.8 V | VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1.2 A | –2% | 2% | ||||
| VDCDC2 = 3.3 V | VCC = 3.7 V to 6 V, 0 mA ≤ IO ≤ 1.2 A | –1% | 1% | |||||
| Fixed output voltage FPWMDCDC2=1 | VDCDC2 = 1.8 V | VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1.2 A | –2% | 2% | ||||
| VDCDC2 = 3.3 V | VCC = 3.7 V to 6 V, 0 mA ≤ IO ≤ 1.2 A | –1% | 1% | |||||
| Adjustable output voltage with resistor divider at DEFDCDC2 FPWMDCDC2 = 0 | VCC = VDCDC2 + 0.3 V (minimum 2.5 V) to 6 V,
0 mA ≤ IO ≤ 1 A |
–2% | 2% | |||||
| Adjustable output voltage with resistor divider at DEFDCDC2, FPWMDCDC2 = 1 | VCC = VDCDC2 + 0.3 V (minimum 2.5 V) to 6 V,
0 mA ≤ IO ≤ 1 A |
–1% | 1% | |||||
| Line regulation | VCC = VDCDC2 + 0.3 V (minimum. 2.5 V) to 6 V, IO = 10 mA | 0 | %/V | |||||
| Load regulation | IO = 10 mA to 1000 mA | 0.25 | %/A | |||||
| Soft-start ramp time | VDCDC2 ramping from 5% to 95% of target value | 750 | μs | |||||
| Internal resistance from L2 to GND | 1 | MΩ | ||||||
| VDCDC2 discharge resistance | DCDC2 discharge = 1 | 300 | Ω | |||||
| VDCDC3 STEP-DOWN CONVERTER | ||||||||
| IO | Maximum output current | DEFDCDC3 = GND | 1000 | mA | ||||
| VCC = 3.6 V, 3.3 V – 1% ≤ VDCDC3 ≤ 3.3 V + 1% | 525 | |||||||
| I(SD) | Shutdown supply current in VINDCDC3 | DCDC3_EN = GND | 0.1 | 1 | μA | |||
| rDS(on) | P-channel MOSFET on-resistance | VCC = V(GS) = 3.6 V | 310 | 698 | mΩ | |||
| Ilkg | P-channel leakage current | VCC = 6 V | 0.1 | 2 | μA | |||
| rDS(on) | N-channel MOSFET on-resistance | VCC = V(GS) = 3.6 V | 220 | 503 | mΩ | |||
| Ilkg | N-channel leakage current | V(DS) = 6 V | 7 | 10 | μA | |||
| Forward current limit (P-channel and N-channel) | 2.5 V < VCC < 6 V | 1.28 | 1.49 | 1.69 | A | |||
| fS | Oscillator frequency | 1.95 | 2.25 | 2.55 | MHz | |||
| Fixed output voltage FPWMDCDC3=0 | VDCDC3 = 1.8 V | VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1 A | –2% | 2% | ||||
| VDCDC3 = 3.3 V | VCC = 3.6 V to 6 V, 0 mA ≤ IO ≤ 1 A | –1% | 1% | |||||
| Fixed output voltage FPWMDCDC3=1 | VDCDC3 = 1.8 V | VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1 A | –2% | 2% | ||||
| VDCDC3 = 3.3 V | VCC = 3.6 V to 6 V, 0 mA ≤ IO ≤ 1 A | –1% | 1% | |||||
| Adjustable output voltage with resistor divider at DEFDCDC3 FPWMDCDC3 = 0 | VCC = VDCDC3 + 0.5 V (minimum 2.5 V) to 6 V,
0 mA ≤ IO ≤ 800 mA |
–2% | 2% | |||||
| Adjustable output voltage with resistor divider at DEFDCDC3, FPWMDCDC3 = 1 | VCC = VDCDC3 + 0.5 V (minimum 2.5 V) to 6 V,
0 mA ≤ IO ≤ 800 mA |
–1% | 1% | |||||
| Line regulation | VCC = VDCDC3 + 0.3 V (minimum. 2.5 V) to 6 V, IO = 10 mA | 0 | %/V | |||||
| Load regulation | IO = 10 mA to 1000 mA | 0.25 | %/A | |||||
| Soft-start ramp time | VDCDC3 ramping from 5% to 95% of target value | 750 | μs | |||||
| Internal resistance from L3 to GND | 1 | MΩ | ||||||
| VDCDC3 discharge resistance | DCDC3 discharge = 1 | 300 | Ω | |||||
| VLDO1 AND VLDO2 LOW DROPOUT REGULATORS | ||||||||
| VI | Input voltage range for LDO1, 2 | 1.5 | 6.5 | V | ||||
| VO(LD01) | LDO1 output voltage range | 1 | 3.15 | V | ||||
| VO(LDO2) | LDO2 output voltage range | 1 | 3.3 | V | ||||
| IO | Maximum output current for LDO1, LDO2 | VCC = 1.8 V, VO = 1.3 V | 200 | mA | ||||
| VCC = 1.5 V, VO = 1.3 V | 120 | |||||||
| I(SC) | LDO1 and LDO2 short circuit current limit | V(LDO1) = GND, V(LDO2) = GND | 400 | mA | ||||
| Minimum voltage drop at LDO1, LDO2 | IO = 50 mA, VINLDO = 1.8 V | 120 | mV | |||||
| IO = 50 mA, VINLDO = 1.5 V | 65 | 150 | ||||||
| IO = 200 mA, VINLDO = 1.8 V | 300 | |||||||
| Output voltage accuracy for LDO1, LDO2 | IO = 10 mA | –2% | 1% | |||||
| Line regulation for LDO1, LDO2 | VINLDO = VLDO1,2 + 0.5 V (minimum 2.5 V) to 6.5 V,
IO = 10 mA |
–1% | 1% | |||||
| Load regulation for LDO1, LDO2 | IO = 0 mA to 50 mA | –1% | 1% | |||||
| Regulation time for LDO1, LDO2 | Load change from 10% to 90% | 10 | μs | |||||
| ANALOG SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3 | ||||||||
| VIH | High-level input voltage(2) | 1.3 | VCC | V | ||||
| VIL | Low-level input voltage | 0 | 0.1 | V | ||||
| Input bias current | 0.001 | 0.05 | μA | |||||
| THERMAL SHUTDOWN | ||||||||
| T(SD) | Thermal shutdown | Increasing junction temperature | 160 | °C | ||||
| Thermal shutdown hysteresis | Decreasing junction temperature | 20 | °C | |||||
| INTERNAL UNDERVOLTAGE LOCK OUT | ||||||||
| UVLO | Internal UVLO | VCC falling | –2% | 2.35 | 2% | V | ||
| VUVLO_HYST | Internal UVLO comparator hysteresis | 120 | mV | |||||
| VOLTAGE DETECTOR COMPARATORS | ||||||||
| Comparator threshold
(PWRFAIL_SNS, LOWBAT_SNS) |
Falling threshold | –2% | 1 | 2% | V | |||
| Hysteresis | 40 | 50 | 60 | mV | ||||
| Propagation delay | 25-mV overdrive | 10 | μs | |||||
| POWER GOOD | ||||||||
| VPGOODF | VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, decreasing | –12% | –10% | –8% | ||||
| VPGOODR | VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, increasing | –7% | –5% | –3% | ||||