ZHCS026C December 2010 – February 2016 TPS57060-Q1
PRODUCTION DATA.
- 1 特征
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed Frequency PWM Control
- 7.3.2 Slope Compensation Output Current
- 7.3.3 Low Dropout Operation and Bootstrap Voltage (BOOT)
- 7.3.4 Error Amplifier
- 7.3.5 Voltage Reference
- 7.3.6 Adjusting the Output Voltage
- 7.3.7 Enable and Adjusting Undervoltage Lockout (UVLO)
- 7.3.8 Slow Start and Tracking Pin (SS/TR)
- 7.3.9 Overload Recovery Circuit
- 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- 7.3.11 Overcurrent Protection and Frequency Shift
- 7.3.12 Selecting the Switching Frequency
- 7.3.13 How to Interface to RT/CLK Pin
- 7.3.14 Power Good (PWRGD Pin)
- 7.3.15 Overvoltage Transient Protection
- 7.3.16 Thermal Shutdown
- 7.3.17 Small Signal Model for Loop Response
- 7.3.18 Simple Small-Signal Model for Peak Current-Mode Control
- 7.3.19 Small Signal Model for Frequency Compensation
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Selecting the Switching Frequency
- 8.2.2.2 Output Inductor Selection (LO)
- 8.2.2.3 Output Capacitor
- 8.2.2.4 Catch Diode
- 8.2.2.5 Input Capacitor
- 8.2.2.6 Slow Start Capacitor
- 8.2.2.7 Bootstrap Capacitor Selection
- 8.2.2.8 Undervoltage Lockout Set Point
- 8.2.2.9 Output Voltage and Feedback Resistors Selection
- 8.2.2.10 Compensation
- 8.2.2.11 Discontinuous Mode and Eco Mode Boundary
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
8.2.2.10 Compensation
There are several methods used to compensate DC/DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope compensation is ignored, the actual cross over frequency will usually be lower than the cross over frequency used in the calculations. This method assume the crossover frequency is between the modulator pole and the esr zero and the esr zero is at least 10 times greater the modulator pole. Use SwitcherPro software for a more accurate design.
To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 41 and Equation 42. For Cout, use a derated value of 40 μF. Use equations Equation 43 and Equation 44, to estimate a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is 603 Hz and fzmod is 796 kHz. Equation 43 is the geometric mean of the modulator pole and the esr zero and Equation 44 is the mean of modulator pole and the switching frequency. Equation 43 yields 21.9 kHz and Equation 44 gives 12.3 kHz. Use the lower value of Equation 43 or Equation 44 for an initial crossover frequency. For this example, fco is 12.3 kHz. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole.
To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance, gmps, is 1.9 A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3 V, 0.8 V and 97 μA/V, respectively. R4 is calculated to be 72.6 kΩ, use the nearest standard value of 73.2 kΩ. Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 3600 pF for compensating capacitor C7, a 3300 pF is used on the board.
Use the larger value of Equation 47 and Equation 48 to calculate the C8, to set the compensation pole. Equation 48 yields 8.7 pF so the nearest standard of 10 pF is used.
