At least 4.7 μF of ceramic type X5R or X7R capacitance is recommended at the output. This output capacitance was selected to meet the requirements for the output ripple (V_rip) and voltage change during a load transient. The loop is then compensated for the selected output capacitor. The output capacitance must be selected based on the most stringent of these criteria. The output ripple voltage is related to the capacitance and equivalent series resistance (ESR) of the output capacitor. Assuming a capacitor with zero ESR, use Equation 20 to calculate the minimum capacitance required for a given ripple. Using high-ESR capacitors causes additional ripple. Use Equation 21 to calculate the maximum ESR for a specified ripple. ESR ripple can be neglected for ceramic capacitors, but must be considered if tantalum or electrolytic capacitors are used. Use Equation 22 to calculate the minimum ceramic output capacitance required to meet a load transient requirement. Use Equation 23 to calculate the RMS current required by the output capacitor for support.

Equation 20.

Equation 21.

Equation 22.

Equation 23.

Using Equation 20 for this design, the minimum output capacitance for the specified 120-mV output ripple is 8.8 μF. For a maximum transient voltage change (ΔV_(TRAN)) of 960 mV with a 400-mA load transient (ΔI_(TRAN)), and a 6-kHz control loop bandwidth (?_BW) with Equation 22, the minimum output capacitance is calculated as 11.1 μF. The most stringent criterion is the 11.1 μF for the required load transient. Equation 23 calculates a 1.58-A RMS current in the output capacitor. The capacitor must also be properly rated for the desired output voltage.

Care must be taken when evaluating ceramic capacitors that derate under DC bias, aging, and AC signal conditions. For example, larger form factor capacitors (in 1206 size) have self-resonant frequencies in the range of the converter switching frequency. Self resonance significantly decreases the effective capacitance. The DC bias also significantly reduces capacitance. Ceramic capacitors can lose as much as 50% of the capacitance when operated at the rated voltage. Therefore, leave a margin when selecting the capacitor voltage rating to ensure adequate capacitance at the required output voltage. For this example, three 4.7-μF, 50-V 1210 X7R ceramic capacitors are used in parallel, leading to a negligible ESR. Selecting 50-V capacitors instead of 35-V capacitors reduces the effects of DC bias and allows this example circuit to be rated for the maximum output voltage range of the TPS55340-Q1 device.