ZHCSQY3 march 2023 TPS546D24S
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Average Current-Mode Control
- 7.3.2 Linear Regulators
- 7.3.3 AVIN and PVIN Pins
- 7.3.4 Input Undervoltage Lockout (UVLO)
- 7.3.5 Start-Up and Shutdown
- 7.3.6 Differential Sense Amplifier and Feedback Divider
- 7.3.7 Set Output Voltage and Adaptive Voltage Scaling (AVS)
- 7.3.8 Prebiased Output Start-Up
- 7.3.9 Soft Stop and (65h) TOFF_FALL Command
- 7.3.10 Power Good (PGOOD)
- 7.3.11 Set Switching Frequency
- 7.3.12 Frequency Synchronization
- 7.3.13 Loop Follower Detection
- 7.3.14 Current Sensing and Sharing
- 7.3.15 Telemetry
- 7.3.16 Overcurrent Protection
- 7.3.17 Overvoltage/Undervoltage Protection
- 7.3.18 Overtemperature Management
- 7.3.19 Fault Management
- 7.3.20 Back-Channel Communication
- 7.3.21 Switching Node (SW)
- 7.3.22 PMBus General Description
- 7.3.23 PMBus Address
- 7.3.24 PMBus Connections
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1 Conventions for Documenting Block Commands
- 7.6.2 (01h) OPERATION
- 7.6.3 (02h) ON_OFF_CONFIG
- 7.6.4 (03h) CLEAR_FAULTS
- 7.6.5 (04h) PHASE
- 7.6.6 (10h) WRITE_PROTECT
- 7.6.7 (15h) STORE_USER_ALL
- 7.6.8 (16h) RESTORE_USER_ALL
- 7.6.9 (19h) CAPABILITY
- 7.6.10 (1Bh) SMBALERT_MASK
- 7.6.11 (1Bh) SMBALERT_MASK_VOUT
- 7.6.12 (1Bh) SMBALERT_MASK_IOUT
- 7.6.13 (1Bh) SMBALERT_MASK_INPUT
- 7.6.14 (1Bh) SMBALERT_MASK_TEMPERATURE
- 7.6.15 (1Bh) SMBALERT_MASK_CML
- 7.6.16 (1Bh) SMBALERT_MASK_OTHER
- 7.6.17 (1Bh) SMBALERT_MASK_MFR
- 7.6.18 (20h) VOUT_MODE
- 7.6.19 (21h) VOUT_COMMAND
- 7.6.20 (22h) VOUT_TRIM
- 7.6.21 (24h) VOUT_MAX
- 7.6.22 (25h) VOUT_MARGIN_HIGH
- 7.6.23 (26h) VOUT_MARGIN_LOW
- 7.6.24 (27h) VOUT_TRANSITION_RATE
- 7.6.25 (29h) VOUT_SCALE_LOOP
- 7.6.26 (2Bh) VOUT_MIN
- 7.6.27 (33h) FREQUENCY_SWITCH
- 7.6.28 (35h) VIN_ON
- 7.6.29 (36h) VIN_OFF
- 7.6.30 (37h) INTERLEAVE
- 7.6.31 (38h) IOUT_CAL_GAIN
- 7.6.32 (39h) IOUT_CAL_OFFSET
- 7.6.33 (40h) VOUT_OV_FAULT_LIMIT
- 7.6.34 (41h) VOUT_OV_FAULT_RESPONSE
- 7.6.35 (42h) VOUT_OV_WARN_LIMIT
- 7.6.36 (43h) VOUT_UV_WARN_LIMIT
- 7.6.37 (44h) VOUT_UV_FAULT_LIMIT
- 7.6.38 (45h) VOUT_UV_FAULT_RESPONSE
- 7.6.39 (46h) IOUT_OC_FAULT_LIMIT
- 7.6.40 (47h) IOUT_OC_FAULT_RESPONSE
- 7.6.41 (4Ah) IOUT_OC_WARN_LIMIT
- 7.6.42 (4Fh) OT_FAULT_LIMIT
- 7.6.43 (50h) OT_FAULT_RESPONSE
- 7.6.44 (51h) OT_WARN_LIMIT
- 7.6.45 (55h) VIN_OV_FAULT_LIMIT
- 7.6.46 (56h) VIN_OV_FAULT_RESPONSE
- 7.6.47 (58h) VIN_UV_WARN_LIMIT
- 7.6.48 (60h) TON_DELAY
- 7.6.49 (61h) TON_RISE
- 7.6.50 (62h) TON_MAX_FAULT_LIMIT
- 7.6.51 (63h) TON_MAX_FAULT_RESPONSE
- 7.6.52 (64h) TOFF_DELAY
- 7.6.53 (65h) TOFF_FALL
- 7.6.54 (78h) STATUS_BYTE
- 7.6.55 (79h) STATUS_WORD
- 7.6.56 (7Ah) STATUS_VOUT
- 7.6.57 (7Bh) STATUS_IOUT
- 7.6.58 (7Ch) STATUS_INPUT
- 7.6.59 (7Dh) STATUS_TEMPERATURE
- 7.6.60 (7Eh) STATUS_CML
- 7.6.61 (7Fh) STATUS_OTHER
- 7.6.62 (80h) STATUS_MFR_SPECIFIC
- 7.6.63 (88h) READ_VIN
- 7.6.64 (8Bh) READ_VOUT
- 7.6.65 (8Ch) READ_IOUT
- 7.6.66 (8Dh) READ_TEMPERATURE_1
- 7.6.67 (98h) PMBUS_REVISION
- 7.6.68 (99h) MFR_ID
- 7.6.69 (9Ah) MFR_MODEL
- 7.6.70 (9Bh) MFR_REVISION
- 7.6.71 (9Eh) MFR_SERIAL
- 7.6.72 (ADh) IC_DEVICE_ID
- 7.6.73 (AEh) IC_DEVICE_REV
- 7.6.74 (B1h) USER_DATA_01 (COMPENSATION_CONFIG)
- 7.6.75 (B5h) USER_DATA_05 (POWER_STAGE_CONFIG)
- 7.6.76 (D0h) MFR_SPECIFIC_00 (TELEMETRY_CONFIG)
- 7.6.77 (DAh) MFR_SPECIFIC_10 (READ_ALL)
- 7.6.78 (DBh) MFR_SPECIFIC_11 (STATUS_ALL)
- 7.6.79 (DCh) MFR_SPECIFIC_12 (STATUS_PHASE)
- 7.6.80 (E3h) MFR_SPECIFIC_19 (PGOOD_CONFIG)
- 7.6.81 (E4h) MFR_SPECIFIC_20 (SYNC_CONFIG)
- 7.6.82 (ECh) MFR_SPECIFIC_28 (STACK_CONFIG)
- 7.6.83 (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS)
- 7.6.84 (EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE)
- 7.6.85 (EFh) MFR_SPECIFIC_31 (DEVICE_ADDRESS)
- 7.6.86 (F0h) MFR_SPECIFIC_32 (NVM_CHECKSUM)
- 7.6.87 (F1h) MFR_SPECIFIC_33 (SIMULATE_FAULT)
- 7.6.88 (FAh) MFR_SPECIFIC_42 (PASSKEY)
- 7.6.89 (FBh) MFR_SPECIFIC_43 (EXT_WRITE_PROTECT)
- 7.6.90 (FCh) MFR_SPECIFIC_44 (FUSION_ID0)
- 7.6.91 (FDh) MFR_SPECIFIC_45 (FUSION_ID1)
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Custom Design With WEBENCH? Tools
- 8.2.2.2 Switching Frequency
- 8.2.2.3 Inductor Selection
- 8.2.2.4 Output Capacitor Selection
- 8.2.2.5 Input Capacitor Selection
- 8.2.2.6 AVIN, BP1V5, VDD5 Bypass Capacitor
- 8.2.2.7 Bootstrap Capacitor Selection
- 8.2.2.8 R-C Snubber
- 8.2.2.9 Output Voltage Setting (VSEL Pin)
- 8.2.2.10 Compensation Selection (MSEL1 Pin)
- 8.2.2.11 Soft Start, Overcurrent Protection, and Stacking Configuration (MSEL2 Pin)
- 8.2.2.12 Enable and UVLO
- 8.2.2.13 ADRSEL
- 8.2.2.14 Pin-Strapping Resistor Selection
- 8.2.2.15 BCX_CLK and BCX_DAT
- 8.2.3 Application Curves
- 8.3
Two-Phase Application
- 8.3.1 Design Requirements
- 8.3.2 Switching Frequency
- 8.3.3 Inductor Selection
- 8.3.4 Output Capacitor Selection
- 8.3.5 Input Capacitor Selection
- 8.3.6 AVIN, BP1V5, VDD5 Bypass Capacitor
- 8.3.7 Bootstrap Capacitor Selection
- 8.3.8 R-C Snubber
- 8.3.9 Output Voltage Setting (VSEL Pin)
- 8.3.10 Compensation Selection (MSEL1 Pin)
- 8.3.11 GOSNS/FLWR Pin of Loop Follower Devices
- 8.3.12 Soft Start, Overcurrent Protection, and Stacking Configuration (MSEL2 Pin)
- 8.3.13 Enable, UVLO
- 8.3.14 VSHARE Pin
- 8.3.15 SYNC Pin
- 8.3.16 VOSNS Pin of Loop Follower Devices
- 8.3.17 Unused Pins of Loop Follower Devices
- 8.3.18 Two-phase Application Curves
- 8.4 Four-Phase Application
- 8.5 Power Supply Recommendations
- 8.6 Layout
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
7.3.1.3 Voltage Error Integrator
The voltage error integrator regulates the output voltage by adjusting the current control voltage, VSHARE, similar to any current mode control architecture. A transconductance amplifier compares the sense feedback voltage to a programmed reference voltage to set the current control voltage VSHARE to maintain the desired output voltage. While a regulated current source feeding an output capacitance provides a natural, stable integrator, mid-band gain is often desired to improve the loop bandwidth and transient response.
With a transconductance set by the current sense gain, the voltage loop cross-over occurs when the full loop gain equal 1 according to Equation 6.
To prevent the current integration loop bandwdith from negatively impacting the phase margin of the voltage loop, the voltage loop must have a target bandwidth of Fcoi / 2.5. With a current mode loop of fSW/4, the voltage loop mid-band gain must be Equation 7:
An integrator pole is necessary to maintain accurate DC regulation, and the zero-frequency set by RVV × CZV must be set below the lowest cross-over frequency with the largest output capacitor intended to be supported at the output, but not more than 1/2 the target voltage loop crossover frequency fcov.
A high frequency noise pole, intended to keep switching noise out of the current loop must also be employed, with a high-frequency pole set by RVV × CPV must be set between fsw/4 and fsw.
For pin programmed options of compensation components, see Table 7-9.
For PMBus programming of compensation values, see (B1h) USER_DATA_01 (COMPENSATION_CONFIG).