ZHCSI03C September 2009 – April 2018 TPS54318
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed Frequency PWM Control
- 7.3.2 Slope Compensation and Output Current
- 7.3.3 Bootstrap Voltage (Boot) and Low Dropout Operation
- 7.3.4 Error Amplifier
- 7.3.5 Voltage Reference
- 7.3.6 Adjusting the Output Voltage
- 7.3.7 Enable and Adjusting Undervoltage Lockout
- 7.3.8 Soft-Start Pin
- 7.3.9 Sequencing
- 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- 7.3.11 Overcurrent Protection
- 7.3.12 Frequency Shift
- 7.3.13 Reverse Overcurrent Protection
- 7.3.14 Synchronize Using the RT/CLK Pin
- 7.3.15 Power Good (PWRGD Pin)
- 7.3.16 Overvoltage Transient Protection
- 7.3.17 Thermal Shutdown
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Step One: Select the Switching Frequency
- 8.2.2.2 Step Two: Select the Output Inductor
- 8.2.2.3 Step Three: Choose the Output Capacitor
- 8.2.2.4 Step Four: Select the Input Capacitor
- 8.2.2.5 Step Five: Minimum Load DC COMP Voltage
- 8.2.2.6 Step Six: Choose the Soft-Start Capacitor
- 8.2.2.7 Step Seven: Select the Bootstrap Capacitor
- 8.2.2.8 Step Eight: Undervoltage Lockout Threshold
- 8.2.2.9 Step Nine: Select Output Voltage and Feedback Resistors
- 8.2.2.10 Step 10: Select Loop Compensation Components
- 8.2.2.11 Power Dissipation Estimate
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
5 Pin Configuration and Functions
RTE Package
16 Pin WQFN
(TOP VIEW)
Pin Functions
| PIN | I/O(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| AGND | 5 | G | Analog ground should be electrically connected to GND close to the device. |
| BOOT | 13 | I | A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed. |
| COMP | 7 | O | Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. |
| EN | 15 | I | Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Can be used to set the on/off threshold (adjust UVLO) with two additional resistors. |
| GND | 3 | G | Power ground. This pin should be electrically connected directly to the power pad under the device. |
| 4 | |||
| PH | 10 | O | The source of the internal high-side power MOSFET, and drain of the internal low-side (synchronous) rectifier MOSFET. |
| 11 | |||
| 12 | |||
| PWRGD | 14 | O | An open drain output, asserts low if output voltage is low due to thermal shutdown, overcurrent, over/under-voltage or EN shut down. |
| RT/CLK | 8 | I/O | Resistor Timing or External Clock input pin. |
| SS | 9 | I/O | Slow-start. An external capacitor connected to this pin sets the output voltage rise time. Soft |
| VIN | 1 | I | Input supply voltage, 2.95 V to 6 V. |
| 2 | |||
| 16 | |||
| VSENSE | 6 | I | Inverting node of the transconductance (gm) error amplifier. |
| Thermal Pad | G | GND pin should be connected to the exposed power pad for proper operation. This power pad should be connected to any internal PCB ground plane using multiple vias for good thermal performance. | |
(1) I = Input, O = Output, G = Ground