ZHCSI03C September 2009 – April 2018 TPS54318
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed Frequency PWM Control
- 7.3.2 Slope Compensation and Output Current
- 7.3.3 Bootstrap Voltage (Boot) and Low Dropout Operation
- 7.3.4 Error Amplifier
- 7.3.5 Voltage Reference
- 7.3.6 Adjusting the Output Voltage
- 7.3.7 Enable and Adjusting Undervoltage Lockout
- 7.3.8 Soft-Start Pin
- 7.3.9 Sequencing
- 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- 7.3.11 Overcurrent Protection
- 7.3.12 Frequency Shift
- 7.3.13 Reverse Overcurrent Protection
- 7.3.14 Synchronize Using the RT/CLK Pin
- 7.3.15 Power Good (PWRGD Pin)
- 7.3.16 Overvoltage Transient Protection
- 7.3.17 Thermal Shutdown
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Step One: Select the Switching Frequency
- 8.2.2.2 Step Two: Select the Output Inductor
- 8.2.2.3 Step Three: Choose the Output Capacitor
- 8.2.2.4 Step Four: Select the Input Capacitor
- 8.2.2.5 Step Five: Minimum Load DC COMP Voltage
- 8.2.2.6 Step Six: Choose the Soft-Start Capacitor
- 8.2.2.7 Step Seven: Select the Bootstrap Capacitor
- 8.2.2.8 Step Eight: Undervoltage Lockout Threshold
- 8.2.2.9 Step Nine: Select Output Voltage and Feedback Resistors
- 8.2.2.10 Step 10: Select Loop Compensation Components
- 8.2.2.11 Power Dissipation Estimate
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.4.3 Small Signal Model for Frequency Compensation
The TPS54318 device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits. The compensation circuits are shown in Figure 34. The Type-II circuits are most likely implemented in high bandwidth power supply designs using low ESR output capacitors. In Type-IIA, one additional high frequency pole is added to attenuate high-frequency noise.
Figure 34. Types of Frequency Compensation
The design guidelines for TPS54318 device loop compensation are as follows:
- Calculate the modulator pole (fP(MOD)) and the esr zero, (fZ1) using Equation 11 and Equation 12. If the output voltage is a high percentage of the capacitor rating it may be necessary to derate the output capacitor (COUT). Use the capacitor manufacturer information to derate the capacitor value. Use Equation 13 and Equation 14 to estimate a starting point for the crossover frequency, fC. Equation 13 shows the geometric mean of the modulator pole and the ESR zero and Equation 14 is the mean of modulator pole and the switching frequency. Use the lower value of Equation 13 or Equation 14 as the maximum crossover frequency.
- Calculate resistor R3. Equation 15 shows the calculation for resistor R3.
- gM(ea) is the amplifier gain (225 μA/V)
- gM(ps) is the power stage gain (13 A/V)
- Place a compensation zero at the dominant pole. fP. Equation 16 shows the calculation for capacitor C1.
- Capacitor C2 is optional. It can be used to cancel the zero from the output capacitor (COUT) ESR.
Equation 11. 
Equation 12. 
Equation 13. 
Equation 14. 
Equation 15. 
where
Equation 16. 
Equation 17. 
Equation 18. 