ZHCS360F July 2012 – November 2020 TPS54020
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Description (Continued)
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Fixed Frequency PWM Control
- 8.3.2 Input Voltage and Power Input Voltage Pins (VIN and PVIN)
- 8.3.3 Voltage Reference (VREF)
- 8.3.4 Adjusting the Output Voltage
- 8.3.5 Safe Start-up into Prebiased Outputs
- 8.3.6 Error Amplifier
- 8.3.7 Slope Compensation
- 8.3.8 Enable and Adjusting Undervoltage Lockout
- 8.3.9 Adjustable Switching Frequency and Synchronization (RT/CLK)
- 8.3.10 Soft-Start (SS) Sequence
- 8.3.11 Power Good (PWRGD)
- 8.3.12 Bootstrap Voltage (BOOT) and Low Dropout Operation
- 8.3.13 Sequencing (SS)
- 8.3.14 Output Overvoltage Protection (OVP)
- 8.3.15 Overcurrent Protection
- 8.3.16 Thermal Shutdown
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Custom Design With WEBENCH? Tools
- 9.2.2.2 Operating Frequency
- 9.2.2.3 Output Inductor Selection
- 9.2.2.4 Output Capacitor Selection
- 9.2.2.5 Input Capacitor Selection
- 9.2.2.6 Soft-Start Capacitor Selection
- 9.2.2.7 Bootstrap Capacitor Selection
- 9.2.2.8 Undervoltage Lockout Set Point
- 9.2.2.9 Output Voltage Feedback Resistor Selection
- 9.2.2.10 Compensation Component Selection
- 9.2.3 Application Curves
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
9.2.2.5 Input Capacitor Selection
The TPS54020 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 μF of effective capacitance on the PVIN input voltage pins and another 4.7 μF on the VIN input voltage pin. In some applications, additional bulk capacitance can also be required for the PVIN input. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple to the device during full load. The input ripple current can be calculated using Equation 26.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 25-V voltage rating is required to support the maximum input voltage. For this example, two 22-μF, 25-V ceramic capacitors and one 68-μF, 25-V electrolytic capacitor in parallel have been selected for the PVIN voltage rail. For the VIN voltage rail, one 4.7-μF, 25-V ceramic capacitor was selected. The VIN and PVIN inputs are normally tied together so the TPS54020 can operate from a single supply. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 27. Using the design example values, IOUT(max) = 10 A, CIN = 48.7 μF, fSW = 500 kHz, yields an input voltage ripple of 103 mV and a RMS input ripple current of 4.18 Arms. Because an electrolytic capacitor typically features a much higher ESR, it was not included in this calculation. The input capacitor ripple voltage is calculated in Equation 27.
