ZHCSHF4J May 2004 – January 2018 TPS51116
PRODUCTION DATA.
請參考 PDF 數據表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY CURRENT | ||||||
| IV5IN1 | Supply current 1, V5IN(1) | TA = 25°C, No load, VS3 = VS5 = 5 V,
COMP connected to capacitor |
0.8 | 2 | mA | |
| IV5IN2 | Supply current 2, V5IN(1) | TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V,
COMP connected to capacitor |
300 | 600 | μA | |
| IV5IN3 | Supply current 3, V5IN(1) | TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V, VCOMP = 5 V | 240 | 500 | ||
| IV5INSDN | Shutdown current, V5IN(1) | TA = 25°C, No load, VS3 = VS5 = 0 V | 0.1 | 1.0 | ||
| IVLDOIN1 | Supply current 1, VLDOIN | TA = 25°C, No load, VS3 = VS5 = 5 V | 1 | 10 | ||
| IVLDOIN2 | Supply current 2, VLDOIN | TA = 25°C, No load, VS3 = 5 V, VS5 = 0 V, | 0.1 | 10 | ||
| IVLDOINSDN | Standby current, VLDOIN | TA = 25°C, No load, VS3 = VS5 = 0 V | 0.1 | 1.0 | ||
| VTTREF OUTPUT | ||||||
| VVTTREF | Output voltage, VTTREF | VVDDQSNS/2 | V | |||
| VVTTREFTOL | Output voltage tolerance | –10 mA < IVTTREF< 10 mA,
VVDDQSNS = 2.5 V, Tolerance to VVDDQSNS/2 |
–20 | 20 | mV | |
| –10 mA < IVTTREF< 10 mA,
VVDDQSNS = 1.8 V, Tolerance to VVDDQSNS/2 |
–18 | 18 | ||||
| –10 mA < IVTTREF< 10 mA,
VVDDQSNS = 1.5 V, Tolerance to VVDDQSNS/2 |
–15 | 15 | ||||
| –10 mA < IVTTREF< 10 mA,
VVDDQSNS = 1.2 V, Tolerance to VVDDQSNS/2 |
–12 | 12 | ||||
| VVTTREFSRC | Source current | VVDDQSNS = 2.5 V, VVTTREF = 0 V | –20 | –40 | –80 | mA |
| VVTTREFSNK | Sink current | VVDDQSNS = 2.5 V, VVTTREF = 2.5 V | 20 | 40 | 80 | |
| VDDQ OUTPUT | ||||||
| VVDDQ | Output voltage, VDDQ | TA = 25°C, VVDDQSET = 0 V, No load | 2.465 | 2.500 | 2.535 | V |
| 0°C ≤ TA ≤ 85°C, VVDDQSET = 0 V, No load(2) | 2.457 | 2.500 | 2.543 | |||
| –40°C ≤ TA ≤ 85°C, VVDDQSET = 0 V, No load (2) | 2.440 | 2.500 | 2.550 | |||
| TA = 25°C, VVDDQSET = 5 V, No load (2) | 1.776 | 1.800 | 1.824 | |||
| 0°C ≤ TA ≤ 85°C, VVDDQSET = 5V, No load(2) | 1.769 | 1.800 | 1.831 | |||
| –40°C ≤ TA ≤ 85°C, VVDDQSET = 5V, No load(2) | 1.764 | 1.800 | 1.836 | |||
| –40°C ≤ TA ≤ 85°C, Adjustable mode, No load(2) | 0.75 | 3.0 | ||||
| VVDDQSET | VDDQSET regulation voltage | TA = 25°C, Adjustable mode | 742.5 | 750.0 | 757.5 | mV |
| 0°C ≤ TA ≤ 85°C, Adjustable mode | 740.2 | 750.0 | 759.8 | |||
| –40°C ≤ TA ≤ 85°C, Adjustable mode | 738.0 | 750.0 | 762.0 | |||
| RVDDQSNS | Input impedance, VDDQSNS | VVDDQSET = 0 V | 215 | kΩ | ||
| VVDDQSET = 5 V | 180 | |||||
| Adjustable mode | 460 | |||||
| IVDDQSET | Input current, VDDQSET | VVDDQSET = 0.78 V, COMP = Open | –0.04 | μA | ||
| VVDDQSET = 0.78 V, COMP = 5 V | –0.06 | |||||
| IVDDQDisch | Discharge current, VDDQ | VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,
VMODE = 0 V |
10 | 40 | mA | |
| IVLDOINDisch | Discharge current, VLDOIN | VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,
VMODE = 0.5 V |
700 | mA | ||
| VTT OUTPUT | ||||||
| VVTTSNS | Output voltage, VTT | VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 2.5 V | 1.25 | V | ||
| VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.8 V | 0.9 | |||||
| VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.5 V | 0.75 | |||||
| VVTTTOL25 | VTT output voltage tolerance to VTTREF | VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V, IVTT = 0 A | –20 | 20 | mV | |
| VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V, |IVTT| < 1.5 A | –30 | 30 | ||||
| VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V, |IVTT| < 3 A | –40 | 40 | ||||
| VVTTTOL18 | VTT output voltage tolerance to VTTREF | VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V, IVTT = 0 A | –20 | 20 | mV | |
| VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V, |IVTT| < 1 A | –30 | 30 | ||||
| VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V, |IVTT| < 2 A | –40 | 40 | ||||
| VVTTTOL15 | VTT output voltage tolerance to VTTREF | VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V, IVTT = 0 A | –20 | 20 | mV | |
| VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V, |IVTT| < 1 A | –30 | 30 | ||||
| VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V, |IVTT| < 2 A | –40 | 40 | ||||
| VVTTTOL12 | VTT output voltage tolerance to VTTREF | VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V, IVTT = 0 A | –20 | 20 | mV | |
| VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V, |IVTT| < 1 A | –30 | 30 | ||||
| VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V, |IVTT| < 1.5 A | –40 | 40 | ||||
| IVTTOCLSRC | Source current limit, VTT | VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS = 1.19 V, PGOOD = HI | 3.0 | 3.8 | 6.0 | A |
| VVLDOIN = VVDDQSNS = 2.5 V, VVTT = 0 V | 1.5 | 2.2 | 3.0 | |||
| IVTTOCLSNK | Sink current limit, VTT | VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS = 1.31 V, PGOOD = HI | 3.0 | 3.6 | 6.0 | |
| VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVDDQ | 1.5 | 2.2 | 3.0 | |||
| IVTTLK | Leakage current, VTT | VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2 | –10 | 10 | μA | |
| IVTTBIAS | Input bias current, VTTSNS | VS3 = 5 V, VVTTSNS = VVDDQSNS /2 | –1 | –0.1 | 1 | |
| IVTTSNSLK | Leakage current, VTTSNS | VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2 | –1 | 1 | ||
| IVTTDisch | Discharge current, VTT | TA = 25°C, VS3 = VS5 = VVDDQSNS = 0 V,
VVTT = 0.5 V |
10 | 17 | mA | |
| TRANSCONDUCTANCE AMPLIFIER | ||||||
| gm | Gain | TA = 25°C | 240 | 300 | 360 | μS |
| ICOMPSNK | COMP maximum sink current | VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.7 V, VCOMP = 1.28 V | 13 | μA | ||
| ICOMPSRC | COMP maximum source
current |
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.3 V, VCOMP = 1.28 V | –13 | |||
| VCOMPHI | COMP high clamp voltage | VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.3 V, VCS = 0 V | 1.31 | 1.34 | 1.37 | V |
| VCOMPLO | COMP low clamp voltage | VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.7 V, VCS = 0 V | 1.18 | 1.21 | 1.24 | |
| DUTY CONTROL | ||||||
| tON | Operating on-time | VIN = 12 V, VVDDQSET = 0 V | 520 | ns | ||
| tON0 | Startup on-time | VIN = 12 V, VVDDQSNS = 0 V | 125 | |||
| tON(min) | Minimum on-time | TA = 25°C(2) | 100 | |||
| tOFF(min) | Minimum off-time | TA = 25°C(2) | 350 | |||
| ZERO CURRENT COMPARATOR | ||||||
| VZC | Zero current comparator offset | –6 | 0 | 6 | mV | |
| OUTPUT DRIVERS | ||||||
| RDRVH | DRVH resistance | Source, IDRVH = –100 mA | 3 | 6 | Ω | |
| Sink, IDRVH = 100 mA | 0.9 | 3 | ||||
| RDRVL | DRVL resistance | Source, IDRVL = –100 mA | 3 | 6 | ||
| Sink, IDRVL = 100 mA | 0.9 | 3 | ||||
| tD | Dead time | LL-low to DRVL-on(2) | 10 | ns | ||
| DRVL-off to DRVH-on(2) | 20 | |||||
| INTERNAL BST DIODE | ||||||
| VFBST | Forward voltage | VV5IN-VBST , IF = 10 mA, TA = 25°C | 0.7 | 0.8 | 0.9 | V |
| IVBSTLK | VBST leakage current | VVBST = 34 V, VLL = 28 V, VVDDQ = 2.6 V,
TA = 25°C |
0.1 | 1.0 | μA | |
| PROTECTIONS | ||||||
| VOCL | Current limit threshold | VPGND-CS , PGOOD = HI, VCS< 0.5 V | 50 | 60 | 70 | mV |
| VPGND-CS , PGOOD = LO, VCS< 0.5 V | 20 | 30 | 40 | |||
| ITRIP | Current sense sink current | TA = 25°C, VCS> 4.5 V, PGOOD = HI | 9 | 10 | 11 | μA |
| TA = 25°C, VCS> 4.5 V, PGOOD = LO | 4 | 5 | 6 | |||
| TCITRIP | TRIP current temperature
coefficient |
RDS(on) sense scheme, On the basis
of TA = 25°C(2) |
4500 | ppm/°C | ||
| VOCL(off) | Overcurrent protection COMP offset | (VV5IN-CS - VPGND-LL), VV5IN-CS = 60 mV,
VCS> 4.5 V (2) |
–5 | 0 | 5 | mV |
| VR(trip) | Current limit threshold setting range | VV5IN-CS(2)(1) | 30 | 150 | ||
| POWERGOOD COMPARATOR | ||||||
| VTVDDQPG | VDDQ powergood threshold | PG in from lower | 92.5% | 95.0% | 97.5% | |
| PG in from higher | 102.5% | 105.0% | 107.5% | |||
| PG hysteresis | 5% | |||||
| IPG(max) | PGOOD sink current | VVTT = 0 V, VPGOOD = 0.5 V | 2.5 | 7.5 | mA | |
| tPG(del) | PGOOD delay time | Delay for PG in | 80 | 130 | 200 | μs |
| UNDERVOLTAGE LOCKOUT/LOGIC THRESHOLD | ||||||
| VUVV5IN | V5IN UVLO threshold
voltage |
Wake up | 3.7 | 4.0 | 4.3 | V |
| Hysteresis | 0.2 | 0.3 | 0.4 | |||
| VTHMODE | MODE threshold | No discharge | 4.7 | |||
| Non-tracking discharge | 0.1 | |||||
| VTHVDDQSET | VDDQSET threshold voltage | 2.5 V output | 0.08 | 0.15 | 0.25 | |
| 1.8 V output | 3.5 | 4.0 | 4.5 | |||
| VIH | High-level input voltage | S3, S5 | 2.2 | |||
| VIL | Low-level input voltage | S3, S5 | 0.3 | |||
| VIHYST | Hysteresis voltage | S3, S5 | 0.2 | |||
| VINLEAK | Logic input leakage current | S3, S5, MODE | –1 | 1 | μA | |
| VINVDDQSET | Input leakage/ bias current | VDDQSET | –1 | 1 | ||
| UNDERVOLTAGE AND OVERVOLTAGE PROTECTION | ||||||
| VOVP | VDDQ OVP trip threshold voltage | OVP detect | 110% | 115% | 120% | |
| Hysteresis | 5% | |||||
| tOVPDEL | VDDQ OVP propagation
delay (2) |
1.5 | μs | |||
| VUVP | Output UVP trip threshold | UVP detect | 70% | |||
| Hysteresis | 10% | |||||
| tUVPDEL | Output UVP propagation delay(2) | 32 | cycle | |||
| tUVPEN | Output UVP enable delay(2) | 1007 | ||||
| THERMAL SHUTDOWN | ||||||
| TSDN | Thermal SDN threshold (2) | Shutdown temperature | 160 | °C | ||
| Hysteresis | 10 | |||||