For MOSFET or Power Block Layout, follow the layout recommendations provided for the MOSFET or Power Block selected.
Connect VDD to VIN as close as possible to the drain connection of the high-side FET to avoid introducing additional drop which could trigger short-circuit protection.
Place VDD and BP to GND capacitors within 2 mm of the device and connected to the Thermal Pad (GND).
The FB to GND resistor should connect to the thermal tab (GND) with a minimum 10-mil wide trace.
Place VOUT to FB resistor within 2 mm of the FB pin.
The EN/SS-to-GND capacitor must connect to the thermal tab (GND) with a minimum 10-mil-wide trace. It may share this trace with FB to GND.
If a BJT or MOSFET is used to disable EN/SS, place it within 5 mm of the device.
If a COMP to GND resistor is used, place it within 5 mm of the device.
All COMP and FB traces should be kept minimum line width and as short as possible to minimize noise coupling.
Do not route EN/SS more than 20 mm from the device.
If multiple layers are used, extend GND under all components connected to FB, COMP and EN/SS to reduce noise sensitivity.
HDRV and LDRV should provide short, low inductance paths of 5 mm or less to the gates of the MOSFETs or Power Block.
No more than 1 Ω of resistance should be placed between HDRV or LDRV and their MOSFET or Power Block gate pins.
LDRV / OC to GND Current Limit Programming resistor may be placed on the far side of the MOSFET if necessary to ensure a short connection from LDRV to the gate of the low-side MOSFET.
The BOOT to SW resistor and capacitor should both be placed within 4 mm of the device using a minimum of 10-mil-wide trace. The full width of the component pads are preferred for trace widths if design rules allow.
If via must be used between the HDRV, SW and LDRV pins and their respective MOSFET or Power Block connections, use a minimum of two vias to reduce parasitic inductance
Refer to the Land Pattern Data for the preferred layout of thermal vias within the thermal pad.
It is recommended to extend the top-layer copper area of the thermal pad (GND) beyond the package a minimum 3 mm between pins 1 and 10 and 5 and 6 to improve thermal resistance to ambient of the device.