ZHCSHA3D NOVEMBER 2009 – March 2018 TPS40303 , TPS40304 , TPS40305
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1
Using the TPS40305 for a 12-V to 1.8-V Point-of-Load Synchronous Buck Regulator
- 8.2.1.1 Design Requirements
- 8.2.1.2
Detailed Design Procedure
- 8.2.1.2.1 Custom Design With WEBENCH® Tools
- 8.2.1.2.2 Selecting the Switching Frequency
- 8.2.1.2.3 Inductor Selection (L1)
- 8.2.1.2.4 Output Capacitor Selection (C12)
- 8.2.1.2.5 Peak Current Rating of Inductor
- 8.2.1.2.6 Input Capacitor Selection (C8)
- 8.2.1.2.7 MOSFET Switch Selection (Q1 and Q2)
- 8.2.1.2.8 Bootstrap Capacitor (C6)
- 8.2.1.2.9 VDD Bypass Capacitor (C7)
- 8.2.1.2.10 BP Bypass Capacitor (C5)
- 8.2.1.2.11 Short-Circuit Protection (R11)
- 8.2.1.2.12 Feedback Divider (R4, R5)
- 8.2.1.2.13 Compensation: (C2, C3, C4, R3, R6)
- 8.2.1.3 Application Curves
- 8.2.2
A High-Current, Low-Voltage Design Using the TPS40304
- 8.2.2.1 Design Requirements
- 8.2.2.2
Detailed Design Procedure
- 8.2.2.2.1 Selecting the Switching Frequency
- 8.2.2.2.2 Inductor Selection (L1)
- 8.2.2.2.3 Output Capacitor Selection (C12)
- 8.2.2.2.4 Peak Current Rating of Inductor
- 8.2.2.2.5 Input Capacitor Selection (C8)
- 8.2.2.2.6 MOSFET Switch Selection (Q1 and Q2)
- 8.2.2.2.7 Bootstrap Capacitor (C6)
- 8.2.2.2.8 VDD Bypass Capacitor (C7)
- 8.2.2.2.9 BP Bypass Capacitor (C5)
- 8.2.2.2.10 Short-Circuit Protection (R11)
- 8.2.2.2.11 Feedback Divider (R4, R5)
- 8.2.2.2.12 Compensation: (C2, C3, C4, R3, R6)
- 8.2.2.3 Application Curves
- 8.2.3
A Synchronous Buck Application Using the TPS40303
- 8.2.3.1 Design Requirements
- 8.2.3.2
Detailed Design Procedure
- 8.2.3.2.1 Selecting the Switching Frequency
- 8.2.3.2.2 Inductor Selection (L1)
- 8.2.3.2.3 Output Capacitor Selection (C12)
- 8.2.3.2.4 Peak Current Rating of Inductor
- 8.2.3.2.5 Input Capacitor Selection (C8)
- 8.2.3.2.6 MOSFET Switch Selection (Q1 and Q2)
- 8.2.3.2.7 Bootstrap Capacitor (C6)
- 8.2.3.2.8 VDD Bypass Capacitor (C7)
- 8.2.3.2.9 BP Bypass Capacitor (C5)
- 8.2.3.2.10 Short-Circuit Protection (R11)
- 8.2.3.2.11 Feedback Divider (R4, R5)
- 8.2.3.2.12 Compensation: (C2, C3, C4, R3, R6)
- 8.2.3.3 Application Curves
- 8.2.1
Using the TPS40305 for a 12-V to 1.8-V Point-of-Load Synchronous Buck Regulator
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.3.5 Overcurrent Protection
Programmable OCP level at LDRV is from 6 mV to 150 mV at room temperature with 3000 ppm temperature coefficient to help compensate for changes in the low-side FET channel resistance as temperature increases. With a scale factor of 2, the actual trip point across the low-side FET is in the range of 12 mV to 300 mV. The accuracy of the internal current source is ±5%. Overall offset voltage, including the offset voltage of the internal comparator and the amplifier for scale factor of 2, is limited to ±8 mV.
Maximum clamp voltage at LDRV is 340 mV to avoid turning on the low-side FET during calibration and in a prebiased condition. The maximum clamp voltage is fixed and it does not change with temperature. If the voltage drop across ROCSET reaches the 340-mV maximum clamp voltage during calibration (no ROCSET resistor included), it disables OC protection. Once disabled, there is no low-side or high-side current sensing.
OCP level at HDRV is fixed at 450 mV with 3000-ppm temperature coefficient to help compensate for changes in the high-side FET channel resistance as temperature increases. OCP at HDRV provides pulse-by-pulse current limiting.
OCP sensing at LDRV is a true inductor valley current detection, using sample and hold. Equation 2 can be used to calculate ROCSET:
where
- IOCSET is the internal current source.
- VOCLOS is the overall offset voltage.
- IP-P is the peak-to-peak inductor current.
- RDS(on) is the drain to source ON-resistance of the low-side FET.
- IOUT(max) is the trip point for OCP.
- ROCSET is the resistor used for setting the OCP level.
To avoid overcurrent tripping in normal operating load range, calculate ROCSET using the equation above with:
- The maximum RDS(ON) at room temperature
- The lower limit of VOCLOS (–8 mV) and the lower limit of IOCSET (9.5 µA) from the Electrical Characteristics table.
- The peak-to-peak inductor current IP-P at minimum input voltage
Overcurrent is sensed across both the low-side FET and the high-side FET. If the voltage drop across either FET exceeds the OC threshold, a count increments one count. If no OC is detected on either FET, the fault counter decrements by one count. If three OC pulses are summed, a fault condition is declared which cycles the soft-start function in a hiccup mode. Hiccup mode consists of four dummy soft-start timeouts followed by a real one if overcurrent condition is encountered during normal operation, or five dummy soft-start timeouts followed by a real one if overcurrent condition occurs from the beginning during start. This cycle continues indefinitely until the fault condition is removed.