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ZHCSTJ7A October 2023 – December 2023 TPS3762

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DDF|8
- MPDS569D

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

6.5 Electrical Characteristics

At V_DD(MIN) ≤ V_DD ≤ V_DD_(MAX), CTR = CTS = open, output RESET pull-up resistor R_PU = 10 kΩ, voltage V_PU= 5.5 V, output BIST pull-up resistor R_{PU_BIST} = 10 kΩ, voltage V_{PU_BIST}= 5.5 V, and load C_LOAD = 10 pF. The operating free-air temperature range T_A = – 40°C to 125°C, unless otherwise noted. Typical values are at T_A = 25°C and V_DD = 12 V and V_IT = 6.5 V (V_IT refers to V_ITN or V_ITP).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLY
V_DD	Supply Voltage		2.7		65	V
UVLO ⁽¹⁾	Undervoltage Lockout	V_DDrising above V_{DD (MIN)}			2.6	V
UVLO(HYS) ⁽¹⁾	Undervoltage Lockout Hysteresis	V_DDfalling below V_{DD (MIN)}		500		mV
V_POR(RESET)	Power on Reset Voltage ⁽²⁾ RESET, Active Low (Open-Drain)	V_OL(MAX) = 300 mV I_{OUT (Sink)} = 15 μA			1.4	V
V_POR(BIST)	Power on Reset Voltage ⁽²⁾ BIST, Active Low (Open-Drain)	V_OL(MAX) = 300 mV I_{OUT (Sink)} = 15 μA			1.4	V
I_DD	Supply current into V_DD pin	V_IT = 800 mV V_{DD (MIN)} ≤ V_DD ≤ V_DD_(MAX)		4	8.1	μA
SENSE (Input)
I_SENSE	Input current	V_IT = 800 mV			200	nA
V_ITN	Input Threshold Negative (Undervoltage)	V_IT = 800 mV ⁽³⁾	-0.9		0.9	%
V_ITP	Input Threshold Positive (Overvoltage)	V_IT = 800 mV ⁽³⁾	-0.9		0.9	%
V_HYS	Hysteresis Accuracy ⁽⁴⁾	V_IT = 0.8 V V_HYS Range = 2%	1.5	2	2.5	%
RESET (Output)
I_lkg(OD)	Open-Drain leakage	V_RESET = 5.5 V V_ITN< V_SENSE < V_ITP			300	nA
I_lkg(OD)	Open-Drain leakage	V_RESET = 65 V V_ITN< V_SENSE < V_ITP			300	nA
V_OL ⁽⁵⁾	Low level output voltage	2.7 V ≤ VDD ≤ 65 V I_RESET= 2.7 mA			350	mV
Capacitor Timing (CTS, CTR)
R_CTR	Internal resistance (CTR)		3.2	4	4.8	M?
R_CTS	Internal resistance (CTS)		3.2	4	4.8	M?
Built-in Self-test
I_lkg(BIST)	Open-Drain leakage	V_BIST = 5.5 V V_ITN< V_SENSE < V_ITP			300	nA
I_lkg(BIST)	Open-Drain leakage	V_BIST = 3.3 V V_ITN< V_SENSE < V_ITP			300	nA
V_{BIST_OL}	Low level output voltage	2.7 V ≤ VDD ≤ 65 V I_BIST= 5 mA			300	mV
V_{BIST_EN}	BIST_EN pin logic low input				500	mV
V_{BIST_EN}	BIST_EN pin logic high input		1300			mV
V_{BIST_EN/LATCH_CLR}	LATCH_CLR pin logic low input				500	mV
V_{BIST_EN/LATCH_CLR}	LATCH_CLR pin logic high input		1300			mV

(1) When V_DD voltage falls below UVLO, RESET is asserted. V_DD slew rate ≤ 100 mV / μs

(2) V_POR is the minimum V_DD voltage for a controlled output state. Below V_POR, the output cannot be determined. V_DD slew rate ≤ 100mV/μs

(3) For adjustable voltage guidelines and resistor selection refer to Adjustable Voltage Thresholds in Application and Implementation section

(4) Hysteresis is with respect to V_ITP and V_ITNvoltage threshold. V_ITP has negative hysteresis and V_ITN has positive hysteresis.

(5) For V_OH and V_OL relation to output variants refer to Timing Figures after the Timing Requirement Table