ZHCSTJ7A October 2023 – December 2023 TPS3762
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Device Comparison
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- DDF|8
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
6.8 Timing Diagrams
A. The timing diagram assumes the open-drain output RESET pin is connected via an external pull-up resistor to VDD.
B. Be advised that Figure 6-1 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTR) time.
C. RESET is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTR, is reached.
Figure 6-1 SENSE Undervoltage (UV) Timing Diagram
A. The timing diagram assumes the open-drain output RESET pin is connected via an external pull-up resistor to VDD.
B. Be advised that Figure 6-2 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTR) time.
C. RESET is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTR, is reached.
Figure 6-2 SENSE Overvoltage (OV) Timing Diagram