ZHCSTJ7A October 2023 – December 2023 TPS3762
PRODUCTION DATA
Built-In Self-Test (BIST) is asserted on device power-up, as outlined in Figure 7-7. BIST can also be initiated any time by a rising edge that crosses the voltage logic high input (VBIST_EN or VBIST_EN/LATCH_CLR > 1.3 V) on the BIST_EN / LATCH_CLR pin, as outlined in Figure 7-8. Output reset latching is set by the device variant. For the device variant used in this design, TPS3762D02OVDDFR, the output has latch. Device specific output reset latching feature can be found in Figure 4-1. In order to clear the latch a logic high input on the BIST_EN / LATCH_CLR pin is required. When clearing latch, BIST is initiated and the RESET returns logic level high once tBIST + tBIST_recover + tCTR has expired, outlined in Figure 7-6. While VBIST_EN/LATCH_CLR > 1.3 V, the device is in latch disabled mode and the RESET will not latch for OV and UV on SENSE pin. While the device is in latch disabled mode the RESET will still assert for OV and UV faults.