SLVSBR5C December 2012 – June 2015 TPS27082L
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
-
8 Application and Implementation
- 8.1 Application Information
- 8.2 Typical Application
- 8.3
System Examples
- 8.3.1 TFT LCD Module Inrush Current Control
- 8.3.2 Standby Power Isolation
- 8.3.3 Boost Regulator With True Shutdown
- 8.3.4 Single Module Multiple Power Supply Sequencing
- 8.3.5 Multiple Modules Interdependent Power Supply Sequencing
- 8.3.6 Multiple Modules Interdependent Supply Sequencing Without a GPIO Input
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
6 Specifications
6.1 Absolute Maximum Ratings
Specified at TJ = –40°C to 125°C (unless otherwise noted)(1)(3)(5)| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| VINmax, VOUTmax |
VIN, VOUT pin maximum voltage with respect to GND pin | –0.1 | 8 | V | |
| VON/OFF | ON/OFF control voltage | –0.3 | 8 | V | |
| IQ1-ON | Max continuous drain current of Q1 | 3 | A | ||
| Max pulsed drain current of Q1(2) | 9.5 | ||||
| PD | Max power dissipation at TA = 25°C, TJ = 150°C(2) | 6 Pin-TSOT, RθJA =105°C/W | 1190 | mW | |
| TA | Operating free-air ambient temperature | -40 | 125(4) | °C | |
| TJ-max | Operating virtual junction temperature | 150 | °C | ||
| Tstg | Storage temperature | –65 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse Width < 300µs, Duty Cycle < 2%
(3) Operating at the absolute TJ-max of 150°C can affect reliability – for higher reliability it is recommended to ensure TJ < 125°C
(4) TJ-max limits and other related conditions apply. Refer to SOA charts, Figure 8 through Figure 13
(5) Refer to TI’s design support web page at www.ti.com/thermal for improving device thermal performance.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VIN | Input Voltage Range | 1 | 8 | V |
| TA | Operating free-air ambient temperature range | -40 | 85 | °C |
| TJ | Junction Temperature | -40 | 105 | °C |
6.4 Thermal Information
| THERMAL METRIC(1) | TPS27082L | UNIT | |
|---|---|---|---|
| DDC (SOT) | |||
| 6 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 105 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 43 | °C/W |
| RθJB | Junction-to-board thermal resistance | 17.8 | °C/W |
| ψJT | Junction-to-top characterization parameter | 6.5 | °C/W |
| ψJB | Junction-to-board characterization parameter | 16.2 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
Full temperature range spans TJ = –40°C to 125°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | TA =TJ = 25°C | FULL TEMP RANGE(1) | UNIT | ||||
|---|---|---|---|---|---|---|---|---|
| MIN | TYP | MAX | MIN | MAX | ||||
| OFF CHARACTERISTICS | ||||||||
| BVIN | VIN breakdown voltage | VON/OFF = 0 V, VGS(Q1) = 0 V, ID(Q1) = 250 µA |
–8 | –8 | V | |||
| IFIN | VIN pin total forward leakage current(5) | VIN = 8 V, ON/OFF = 0 V, RL = 2.5 Ω |
0.15 | 30 | µA | |||
| VIN = 5 V, ON/OFF = 0 V, RL = 2.5 Ω |
0.04 | 12 | ||||||
| ON CHARACTERISTICS(2) | ||||||||
| VT+
(VIH) |
Positive going ON/OFF threshold voltage(3) | VIN = 5.0 V, R1 = 125 kΩ(1), RL = 2.5 Ω |
1.0 | V | ||||
| VIN = 5.0 V, R1 = 1 MΩ, RL = 2.5 Ω |
1.0 | |||||||
| VT–
(VIL) |
Negative going ON/OFF threshold voltage(3) | VIN = 5.0 V, ID(Q1) < 175 µA, R1 =125 kΩ(1) |
400 | mV | ||||
| VIN = 5.0 V, ID(Q1) < 175 µA, R1 = 1 MΩ |
270 | |||||||
| ?VT
(VT+–VT–) |
ON/OFF input logic hysteresis(3) | VIN = 5.0 V, R1 = 125 kΩ(1) | 600 | mV | ||||
| VIN = 5.0 V, R1 = 1 MΩ | 730 | |||||||
| RQ1(ON) | Q1 Channel ON resistance(4) | VGSQ1 = –4.5V, ID = 3.0 A | 32 | 52 | 64 | mΩ | ||
| VGS1Q1 = -3.0V, ID =2 .5 A | 44 | 66 | 84 | |||||
| VGS1Q1 = -2.5V, ID = 2.5 A | 50 | 76 | 92 | |||||
| VGSQ1 = -1.8V, ID = 2.0 A | 82 | 113 | 147 | |||||
| VGSQ1 = -1.5V, ID = 1.0 A | 97 | 150 | 173 | |||||
| VGSQ1 = -1.2V, ID = 0.50 A | 155 | 250 | 260 | |||||
| RGNDON | R1/C1 pin to GND pin resistance when Q2 is ON | VON/OFF = 1.8 V | 12.5 | 14.2 | 14.5 | kΩ | ||
| Q1 DRAIN-SOURCE DIODE PARAMETERS(1)(2)(6) | ||||||||
| IFSD | Source-drain diode peak forward current | VFSD(Q1) = 0.8V, VON/OFF = 0 V | 1 | A | ||||
| VFSD | Source-drain diode forward voltage | IFSD(Q1) = -0.6A, VON/OFF = 0 V | 1.0 | V | ||||
(1) Specified by design only
(2) Pulse width < 300µs, Duty cycle < 2%
(3) Refer to charts for more information on VT+/VT– thresholds
(4) Refer to SOA charts for operating current information
(5) Refer to IFVIN plots for more information
(6) Not rated for continuous current operation
6.6 Dissipation Ratings
See (1)(4)(3).| BOARD | PACKAGE | RθJC | RθJA(2) | TA < 25°C | TA = 70°C | TA = 85°C | TA = 105°C | DERATING FACTOR ABOVE TA = 25°C |
|---|---|---|---|---|---|---|---|---|
| High-K (JEDEC 51-7) |
6-Pin TSOT (DDC) |
43°C/W | 105°C/W | 1190 mW | 760 mW | 619 mW | 428 mW | 9.55 mW/°C |
(1) Maximum dissipation values for retaining a maximum allowable device junction temperature of 150°C
(2) Operating at the absolute TJ-max of 150°C can affect reliability; TJ ≤ 125°C is recommended
(3) Package thermal data based on a 76x114x1.6mm, 4-layer board with 2-oz Copper on outer layers
(4) Refer to TI’s design support web page at www.ti.com/thermal for improving device thermal performance
6.7 Typical Characteristics
Figure 1. Vdrop vs IL; VGS_Q1 = –1.2 V
Figure 3. Vdrop vs IL; VGS_Q1 = –2.5 V
Figure 5. Vdrop vs IL; VGS_Q1 = –4.5 V
Figure 7. Vdrop vs IL; VGS_Q1 = –7 V
Figure 2. Vdrop vs IL; VGS_Q1 = –1.8 V
Figure 4. Vdrop vs IL; VGS_Q1 = –3.3 V
Figure 6. Vdrop vs IL; VGS_Q1 = –5.5 V
6.7.1 PFET Q1 Minimum Safe Operating Area (SOA)
(Refer to Dissipation Ratings for PCB details)
Figure 8. Q1 SOA at VGS_Q1=-4.5V
Figure 10. Q1 SOA at VGS_Q1=-2.5V
Figure 12. Q1 SOA at VGS_Q1=-1.5V
Figure 14. ON/OFF Positive and Negative Going Threshold Voltage
Figure 9. Q1 SOA at VGS_Q1=-3.0V
Figure 11. Q1 SOA at VGS_Q1=-1.8V
Figure 13. Q1 SOA at VGS_Q1=-1.2V