10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

• VIN and VOUT traces should be as short and wide as possible to accommodate for high current.
• The VIN pin should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is 1-μF ceramic with X5R or X7R dielectric. This capacitor should be placed as close to the device pins as possible.
• The VOUT pin should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is one-tenth of the VIN bypass capacitor of X5R or X7R dielectric rating. This capacitor should be placed as close to the device pins as possible.

10.2 Layout Example

Figure 23. Layout Diagram

10.3 Thermal Considerations

For higher reliability it is recommended to limit TPS27082L IC’s die junction temperature to less than 125°C. The IC junction temperature is directly proportional to the on-chip power dissipation. Use the following equation to calculate maximum on-chip power dissipation to restrict the die junction temperature target to safe limits:

Equation 6.

where

• T_J(MAX) is the target maximum junction temperature,
• T_A is the operating ambient temperature,
• and R_θJA is the package junction to ambient thermal resistance.