ZHCSGV1C June 2017 – March 2018 TPS25740B
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 ENSRC
- 8.3.2 USB Type-C CC Logic (CC1, CC2)
- 8.3.3 USB PD BMC Transmission (CC1, CC2, VTX)
- 8.3.4 USB PD BMC Reception (CC1, CC2)
- 8.3.5 Discharging (DSCG, VPWR)
- 8.3.6 Configuring Voltage Capabilities (HIPWR)
- 8.3.7 Configuring Power Capabilities (PSEL, PCTRL, HIPWR)
- 8.3.8 Gate Driver (GDNG, GDNS)
- 8.3.9 Fault Monitoring and Protection
- 8.3.10 Voltage Control (CTL1, CTL2,CTL3)
- 8.3.11 Sink Attachment Indicator (DVDD)
- 8.3.12 Power Supplies (VAUX, VDD, VPWR, DVDD)
- 8.3.13 Grounds (AGND, GND)
- 8.3.14 Output Power Supply (DVDD)
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1
Application Information
- 9.1.1 System-Level ESD Protection
- 9.1.2 Using ENSRC to Enable the Power Supply upon Sink Attachment
- 9.1.3 Use of GD Internal Clamp
- 9.1.4 Resistor Divider on GD for Programmable Start Up
- 9.1.5 Selection of the CTL1, CTL2, and CTL3 Resistors (R(FBL1), R(FBL2), and R(FBL3))
- 9.1.6 Voltage Transition Requirements
- 9.1.7 VBUS Slew Control using GDNG C(SLEW)
- 9.1.8 Tuning OCP using RF and CF
- 9.2 Typical Applications
- 9.3 System Examples
- 9.1
Application Information
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
8.3.9.3 System Fault Input (GD, VPWR)
The gate-driver disable pin provides a method of overriding the internal control of GDNG and GDNS. A falling edge on GD disables the gate driver within tGDoff. If GD is held low after a sink is attached for 600 ms then a hard reset will be generated and the device sends a hard reset and go through its startup process again.
The GD input can be controlled by a voltage or current source. An internal voltage clamp is provided to limit the input voltage in current source applications. The clamp can safely conduct up to 80 µA and will remain high impedance up to 6.5 V before clamping.
Figure 36. Overcurrent Protection Circuit, (GD) If the VPWR pin remains below its falling UVLO threshold (V(VPWR_TH)) for more than 600 ms after a sink is attached then the devices consider it a fault and will not enable GDNG. If the VPWR pin is between the rising and falling UVLO threshold, the device may enable GDNG and proceed with normal operations. However, after GDNG is enabled, if the VBUS pin does not rise above its UVLO within 190 ms the devices consider it a fast-shutdown fault and disables GDNG. Therefore, in order to ensure USB Type-C compliance and normal operation, the VPWR pin must be above its rising UVLO threshold (V(VPWR_TH)) within 275 ms of when ENSRC is pulled low and the VBUS pin must be above V(VBUS_RTH) within 190 ms of GDNG being enabled.