ZHCSBP7C October 2013 – December 2018 TPS24750 , TPS24751
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
After the TPS2475x initialization is complete (as described in the Board Plug-in section) and EN is active, GATE is enabled (VGATE starts increasing), when VGATE reaches the internal FET gate threshold, a current flows into the downstream bulk storage capacitors. When this current exceeds the limit set by the power-limit engine, the gate of the internal FET is regulated by a feedback loop to make the internal FET current rise in a controlled manner. This not only limits the capacitor-charging inrush current but it also limits the power dissipation of the internal FET to safe levels. A more complete explanation of the power-limiting scheme is given in the Action of the Constant-Power Engine section. When the GATE is enabled, the TIMER pin begins to charge the timing capacitor CT with a current of approximately 10 µA. The TIMER pin continues to charge CT until V(GATE-VCC) reaches the timer activation voltage (5.8 V for VVCC = 12V). The TIMER then begins to discharge CT with a current of approximately 10 µA. This indicates that the inrush mode is finished. If the TIMER exceeds its upper threshold of 1.35 V before V(GATE – VCC) reaches the timer activation voltage, the GATE pin is pulled to GND and the hot-swap circuit enters either latch mode (TPS24750) or auto-retry mode (TPS24751).
The power limit feature is disabled once the inrush operation is finished and the hotswap circuit becomes a circuit breaker. The TPS2475x turns off the internal FET after a fault timer period once the load exceeds the current limit threshold.